ds1721st-r Maxim Integrated Products, Inc., ds1721st-r Datasheet - Page 13
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ds1721st-r
Manufacturer Part Number
ds1721st-r
Description
Ds1721 Digital Thermometer And Thermostat
Manufacturer
Maxim Integrated Products, Inc.
Datasheet
1.DS1721ST-R.pdf
(17 pages)
SAMPLE COMMAND SEQUENCE Table 6
Example: Bus master programs the DS1721 for 11-bit conversions in the continuous mode with an active
low state for the thermostat output. It then programs TH=50°C and TL=45°C and starts temperature
conversions.
BUS MASTER
MODE
RX
RX
RX
RX
RX
RX
RX
RX
RX
RX
RX
RX
RX
TX
TX
TX
TX
TX
TX
TX
TX
TX
TX
TX
TX
TX
TX
TX
TX
TX
TX
DS1721
MODE
RX
RX
RX
RX
RX
RX
RX
RX
RX
RX
RX
RX
RX
RX
RX
RX
RX
RX
TX
TX
TX
TX
TX
TX
TX
TX
TX
TX
TX
TX
TX
DATA (MSB
<address, 0>
<address, 0>
<address, 0>
<address, 0>
FIRST)
START
START
START
START
STOP
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACh
A1h
A2h
2Dh
08h
32h
00h
00h
51h
13 of 17
COMMENTS
Bus Master initiates a START condition
Bus Master sends DS1721 address; R/
DS1721 generates acknowledge bit
Bus Master sends access configuration protocol
DS1721 generates acknowledge bit
Bus Master programs configuration register as
described above. This will also clear thermostat
flags
DS1721 generates acknowledge bit
Bus Master Initiates a REPEATED START
condition
Bus Master sends DS1721 address; R/
DS1721 generates acknowledge bit
Bus Master sends access TH protocol
DS1721 generates acknowledge bit
Bus Master writes MSB of TH (50°C)
DS1721 generates acknowledge bit
Bus Master writes LSB of TH (50°C)
DS1721 generates acknowledge bit
Bus Master initiates a REPEATED START
condition
Bus Master sends DS1721 address; R/
DS1721 generates acknowledge bit
Bus Master sends access TL protocol
DS1721 generates acknowledge bit
Bus Master writes MSB of TL (45°C)
DS1721 generates acknowledge bit
Bus Master writes LSB of TL (45°C)
DS1721 generates acknowledge bit
Bus Master initiates a REPEATED START
condition
Bus Master sends DS1721 address; R/
DS1721 generates acknowledge bit
Bus Master sends start convert protocol
DS1721 generates acknowledge bit
Bus Master initiates STOP condition
W
W
W
W
= 0
= 0
= 0
= 0