ds1721st-r Maxim Integrated Products, Inc., ds1721st-r Datasheet - Page 16
![no-image](/images/no-image-200.jpg)
ds1721st-r
Manufacturer Part Number
ds1721st-r
Description
Ds1721 Digital Thermometer And Thermostat
Manufacturer
Maxim Integrated Products, Inc.
Datasheet
1.DS1721ST-R.pdf
(17 pages)
NOTES:
1. All voltages are referenced to ground.
2. I/O pins of fast mode devices must not obstruct the SDA and SCL lines if V
3. I
4. I
5. After this period, the first clock pulse is generated.
6. The maximum t
7. A fast mode device can be used in a standard mode system, but the requirement t
8. C
TIMING DIAGRAMS Figure 7
Capacitive Load for
each Bus Line
Input Capacitance
SCL signal.
then be met. This will automatically be the case if the device does not stretch the LOW period of the
SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next
data bit to the SDA line t
DD
DD
b
- total capacitance of one bus line in pF.
specified with T
specified with V
HD:DAT
OUT
DD
has only to be met if the device does not stretch the LOW period (t
at 5.0V and SDA,SCL = 5.0V, 0°C to 70°C.
pin open.
C
C
R
b
I
MAX+t
SU:DAT
1000+250 = 1250 ns before the SCL line is released.
16 of 17
5
400
DD
is switched off.
SU:DAT
pF
pF
>250 ns must
LOW
) of the
8