ds1384 Maxim Integrated Products, Inc., ds1384 Datasheet - Page 5

• Manufacturer Part Number: ds1384
• Description: Ds1384 Watchdog Real Time Clocks Controller
• Manufacturer: Maxim Integrated Products, Inc.

contention. However, if the output bus has been enabled (CE and OE active), then WE will disable the
outputs in t
When the address value presented to the DS1384 during the write is in the range of 00000H through
0003FH, one of the 64 on-chip registers will be selected and data will be written into the device.
When the address value presented to the DS1384 during the write is in the range of 00040H through
1FFFFH, an external SRAM location will be selected.
DATA RETENTION MODE
When V
read or write cycles. However, when V
protection occurs) the internal clock registers and external RAM is blocked from access. This is
accomplished internally by inhibiting access to the clock registers via the CE signal. At this time the
power fail output signal (PFO) is driven active and will remain active until V
External RAM access is inhibited in a similar manner by forcing CEO to high level. This level is within
0.2 volts of the V
condition. When V
the V
External RAM is also powered by the V
V
under this condition. On power-up, when V
continues for 150ms by inhibiting CEO. The PFO signal also remains active during this time. The
DS1384 is capable of supporting two batteries which are used in a redundant fashion for applications
which require added reliability or increased battery capacity. When two batteries are used, the higher of
the two is selected for use. A selected battery will remain as backup supply until it is significantly below
the other. When the selected battery voltage falls below the alternate battery by about 0.6V, the alternate
battery is selected and then becomes the backup supply. This switching occurs transparently to the user
and continues until both batteries are exhausted. When only a single battery is required, both battery
inputs can be connected together. However, a more effective method of using a single battery supply is to
ground the unused battery input. When using a single battery, V
WATCHDOG TIMEKEEPER REGISTERS
The DS1384 Watchdog Timekeeper Controller has 14 internal registers, which are 8 bits wide and
contain all of the Timekeeping, Alarm, Watchdog, Control, and Data information. The Clock, Calendar,
Alarm and Watchdog Registers are memory locations, which contain external (user accessible) and
internal copies of the data. The external copies are independent of internal functions except that they are
updated periodically by the simultaneous transfer of the incremented internal copy (see Figure 1). The
Command Register bits are affected by both internal and external functions. This register will be
discussed later. The 50 bytes of RAM registers are accessed from the external address and data bus and
reside or overlay external static RAM. Registers 0, 1, 2, 4, 6, 8, 9 and A contain time of day and date
information (see Figure 2). Time of day information is stored in BCD. Registers 3, 5, and 7 contain the
time of day alarm information. Time of day alarm information is stored in BCD. Register B is the
Command Register and information in this register is binary. Register C and D are the Watchdog Alarm
Registers and information, which is stored in these two registers, is in BCD. Registers 0000EH through
register 0003FH are on-chip user bytes and can be used to contain data at the user’s discretion.
CCO
CCI
pin is capable of supplying 100µA of current to the attached memory with less than 0.3V drop
CCI
pin to the V
WEZ
is within nominal limits (V
from its falling edge.
CCI
CCI
input. CEO will remain at this level as long as V
BAT
falls below the level of the battery (V
pin and the clock registers are maintained from the attached battery supply.
CC
BAT
CC
> 4.5V) the DS1384 can be accessed as described above with
input when V
is below the power-fail point, V
CCI
5 of 18
returns to in-tolerance conditions, write protection
CCI
BAT1
is below V
BAT1
or V
is the preferred input.
BAT2
CCI
BAT
), power input is switched from
remains at an out-of-tolerance
pin through the V
CC
PF
returns to nominal levels.
, (point at which write
CCO
pin. The