74LVT16374MTD Fairchild Semiconductor, 74LVT16374MTD Datasheet

74LVT16374MTD

Manufacturer Part Number

74LVT16374MTD

Description

IC FLIP FLOP 16BIT D 3ST 48TSSOP

Manufacturer

Fairchild Semiconductor

Series

74LVTr

Type

D-Type Busr

Datasheet

1.74LVT16374MTDX.pdf (8 pages)

Specifications of 74LVT16374MTD

Function

Standard

Output Type

Tri-State Non Inverted

Number Of Elements

Number Of Bits Per Element

Frequency - Clock

160MHz

Delay Time - Propagation

4.5ns

Trigger Type

Positive Edge

Current - Output High, Low

32mA, 64mA

Voltage - Supply

2.7 V ~ 3.6 V

Operating Temperature

-40°C ~ 85°C

Mounting Type

Surface Mount

Package / Case

48-TSSOP

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

Meier Automation Equipment Co., Limited

Part Number:

74LVT16374MTDX

Manufacturer:

FAIRCHILD/仙童

Quantity:

20 000

Company:

H&T Electronics

Part Number:

74LVT16374MTDX

Quantity:

4 000

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74LVT16374G

(Note 1)(Note 2)

74LVT16374MEA

(Note 2)

74LVT16374MTD

(Note 2)

74LVTH16374G

(Note 1)(Note 2)

74LVTH16374MEA

(Note 2)

74LVTH16374MTD

(Note 2)

74LVT16374 • 74LVTH16374

Low Voltage 16-Bit D-Type Flip-Flop

with 3-STATE Outputs

General Description

The LVT16374 and LVTH16374 contain sixteen non-invert-

ing D-type flip-flops with 3-STATE outputs and is intended

for bus oriented applications. The device is byte controlled.

A buffered clock (CP) and Output Enable (OE) are com-

mon to each byte and can be shorted together for full 16-bit

operation.

The LVTH16374 data inputs include bushold, eliminating

the need for external pull-up resistors to hold unused

inputs.

These flip-flops are designed for low-voltage (3.3V) V

applications, but with the capability to provide a TTL inter-

face to a 5V environment. The LVT16374 and LVTH16374

are fabricated with an advanced BiCMOS technology to

achieve high speed operation similar to 5V ABT while

maintaining a low power dissipation.

Ordering Code:

Note 1: Ordering code “G” indicates Trays.

Note 2: Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbol

Order Number

Package Number

(Preliminary)

BGA54A

MS48A

MTD48

MS48A

MTD48

54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide

48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide

48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

DS012022

Features

Input and output interface capability to systems at

5V V

Bushold data inputs eliminate the need for external

pull-up resistors to hold unused inputs (74LVTH16374),

also available without bushold feature (74LVT16374)

Live insertion/extraction permitted

Power Up/Power Down high impedance provides

glitch-free bus loading

Outputs source/sink

Functionally compatible with the 74 series 16374

Latch-up performance exceeds 500 mA

ESD performance:

Human-body model

Machine model

Charged-device model

Also packaged in plastic Fine-Pitch Ball Grid Array

(FBGA)

Package Description

200V

32 mA/

2000V

1000V

January 1999

Revised June 2005

64 mA

www.fairchildsemi.com

Related parts for 74LVT16374MTD

74LVT16374MTD Summary of contents

Page 1

... MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide (Note 2) 74LVT16374MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide (Note 2) 74LVTH16374G BGA54A 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide ...

Page 2

Connection Diagrams Pin Assignment for SSOP and TSSOP Pin Assignment for FBGA (Top Thru View) Functional Description The LVT16374 and LVTH16374 consist of sixteen edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The device is byte controlled with ...

Page 3

Logic Diagrams Please note that these diagrams are provided for the understanding of logic operation and should not be used to estimate propagation delays. Byte 1 (0:7) Byte 2 (8:15) 3 www.fairchildsemi.com ...

Page 4

Absolute Maximum Ratings Symbol Parameter V Supply Voltage Input Voltage Output Voltage Input Diode Current Output Diode Current Output Current Supply Current ...

Page 5

DC Electrical Characteristics Symbol Parameter I Power Supply Current CCH I Power Supply Current CCL I Power Supply Current CCZ I Power Supply Current CCZ ' I Increase in Power Supply Current CC (Note 8) Note 5: Applies to ...

Page 6

Physical Dimensions inches (millimeters) unless otherwise noted 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide www.fairchildsemi.com Package Number BGA54A 6 ...

Page 7

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide Package Number MS48A 7 www.fairchildsemi.com ...

Page 8

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves ...

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