74LVT125DB,112 NXP Semiconductors, 74LVT125DB,112 Datasheet

IC BUFF TRI-ST QD N-INV 14SSOP

74LVT125DB,112

Manufacturer Part Number
74LVT125DB,112
Description
IC BUFF TRI-ST QD N-INV 14SSOP
Manufacturer
NXP Semiconductors
Series
74LVTr
Datasheet

Specifications of 74LVT125DB,112

Logic Type
Buffer/Line Driver, Non-Inverting
Number Of Elements
4
Number Of Bits Per Element
1
Current - Output High, Low
32mA, 64mA
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
14-SSOP
Logic Family
LVT
Number Of Channels Per Chip
4
Polarity
Non-Inverting
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.7 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
High Level Output Current
- 32 mA
Low Level Output Current
64 mA
Minimum Operating Temperature
- 40 C
Number Of Lines (input / Output)
4 / 4
Output Type
3-State
Propagation Delay Time
2.9 ns at 3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
74LVT125DB
74LVT125DB
935180980112

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
74LVT125DB,112
Manufacturer:
Nexperia USA Inc.
Quantity:
486
1. General description
2. Features
3. Quick reference data
The 74LVT125; 74LVTH125 is a high-performance BiCMOS product designed for V
operation at 3.3 V.
This device combines low static and dynamic power dissipation with high speed and high
output drive. The 74LVT125; 74LVTH125 device is a quad buffer that is ideal for driving
bus lines. The device features four output enable inputs (1OE, 2OE, 3OE and 4OE), each
controlling one of the 3-state outputs.
I
I
I
I
I
I
I
I
I
I
I
Table 1.
GND = 0 V; T
Symbol Parameter
t
t
PLH
PHL
74LVT125; 74LVTH125
3.3 V quad buffer; 3-state
Rev. 06 — 6 March 2006
Quad bus interface
3-state buffers
Output capability: +64 mA and 32 mA
TTL input and output switching levels
Input and output interface capability to systems at 5 V supply
Bus hold data inputs eliminate need for external pull-up resistors to hold unused inputs
Live insertion and extraction permitted
No bus current loading when output is tied to 5 V bus
Power-up 3-state
Latch-up protection:
ESD protection:
N
N
N
MIL STD 883 method 3015: exceeds 2000 V
Machine model: exceeds 200 V
JESD78: exceeds 500 mA
LOW-to-HIGH propagation
delay nA to nY
HIGH-to-LOW propagation
delay nA to nY
Quick reference data
amb
= 25 C.
Conditions
C
C
L
L
= 50 pF; V
= 50 pF; V
CC
CC
= 3.3 V
= 3.3 V
Min
-
-
Product data sheet
Typ
2.7
2.9
Max
-
-
Unit
ns
ns
CC

74LVT125DB,112 Summary of contents

Page 1

V quad buffer; 3-state Rev. 06 — 6 March 2006 1. General description The 74LVT125; 74LVTH125 is a high-performance BiCMOS product designed for V operation at 3.3 V. This device combines low static and dynamic power dissipation ...

Page 2

Philips Semiconductors Table 1. GND = Symbol Parameter Ordering information Table 2. Ordering information Type number Package Temperature range Name 74LVT125D +85 C 74LVT125DB ...

Page 3

Philips Semiconductors 5. Functional diagram Fig 1. Logic symbol Fig 3. Logic diagram 6. Pinning information 6.1 Pinning Fig 4. Pin configuration SO14, SSOP14 74LVT_LVTH125_6 Product data sheet 1OE 2OE 4 ...

Page 4

Philips Semiconductors 6.2 Pin description Table 3. Symbol 1OE 1A 1Y 2OE 2A 2Y GND 3Y 3A 3OE 4Y 4A 4OE Functional description 7.1 Function table Table 4. Control nOE HIGH voltage ...

Page 5

Philips Semiconductors 8. Limiting values Table 5. In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter ...

Page 6

Philips Semiconductors 10. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter [ +85 C amb V input clamping voltage IK V HIGH-state ...

Page 7

Philips Semiconductors Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter I additional quiescent supply CC current C input capacitance i C output capacitance o [1] Typical values are measured ...

Page 8

Philips Semiconductors 12. Waveforms Fig 6. Propagation delay input (nA) to output (nY) Fig 7. Enable and disable times of 3-state outputs 74LVT_LVTH125_6 Product data sheet input GND t PLH output ...

Page 9

Philips Semiconductors Fig 8. Load circuitry for switching times Table 9. Input V I 2.7 V 74LVT_LVTH125_6 Product data sheet negative V M pulse ...

Page 10

Philips Semiconductors 13. Package outline SO14: plastic small outline package; 14 leads; body width 3 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT ...

Page 11

Philips Semiconductors SSOP14: plastic shrink small outline package; 14 leads; body width 5 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.21 1.80 mm ...

Page 12

Philips Semiconductors TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 ...

Page 13

Philips Semiconductors DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2 0.85 mm terminal 1 index area terminal 1 index area ...

Page 14

Philips Semiconductors 14. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge TTL Transistor-Transistor Logic 15. Revision history Table 11. Revision history Document ID Release date 74LVT_LVTH125_6 20060306 • Modifications: Section ...

Page 15

Philips Semiconductors 16. Legal information 16.1 Data sheet status [1][2] Document status Product status Objective [short] data sheet Development Preliminary [short] data sheet Qualification Product [short] data sheet Production [1] Please consult the most recently issued document before initiating or ...

Page 16

Philips Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . ...

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