74LVT16374MTD Fairchild Semiconductor, 74LVT16374MTD Datasheet - Page 2

• Manufacturer Part Number: 74LVT16374MTD
• Description: IC FLIP FLOP 16BIT D 3ST 48TSSOP
• Manufacturer: Fairchild Semiconductor
• Series: 74LVTr
• Type: D-Type Busr

Specifications of 74LVT16374MTD

• Function: Standard
• Output Type: Tri-State Non Inverted
• Number Of Elements: 2
• Number Of Bits Per Element: 8
• Frequency - Clock: 160MHz
• Delay Time - Propagation: 4.5ns
• Trigger Type: Positive Edge
• Current - Output High, Low: 32mA, 64mA
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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Connection Diagrams
Functional Description
The LVT16374 and LVTH16374 consist of sixteen
edge-triggered flip-flops with individual D-type inputs and
3-STATE true outputs. The device is byte controlled with
each byte functioning identically, but independent of the
other. The control pins can be shorted together to obtain
full 16-bit operation. Each byte has a buffered clock and
buffered Output Enable common to all flip-flops within that
byte. The description which follows applies to each byte.
Pin Assignment for SSOP and TSSOP
Pin Assignment for FBGA
(Top Thru View)
2
Pin Descriptions
FBGA Pin Assignments
Truth Tables
H
L
X
Z
O
Each flip-flop will store the state of their individual D-type
inputs that meet the setup and hold time requirements on
the LOW-to-HIGH Clock (CP
Enable (OE
able at the outputs. When OE
the high impedance state. Operation of the OE
not affect the state of the flip-flops.
OE
CP
I
O
NC
o
0
–I
0
LOW Voltage Level
HIGH Impedance
HIGH Voltage Level
Immaterial
Pin Names
–O
Previous O
n
G
n
A
B
C
D
E
F
H
15
J
CP
CP




X
X
L
L
15
2
1
O
O
O
O
n
O
O
O
O
O
) LOW, the contents of the flip-flops are avail-
o
1
10
12
14
15
0
2
4
6
8
before HIGH to LOW of CP
OE
Inputs
Clock Pulse Input
No Connect
OE
Inputs
Output Enable Input (Active LOW)
Inputs
3-STATE Outputs
H
L
L
L
H
L
L
L
O
O
NC
NC
O
O
O
O
O
2
2
1
11
13
1
3
5
7
9
GND
GND
GND
OE
OE
V
V
NC
NC
n
3
CC
CC
n
) transition. With the Output
1
2
I
is HIGH, the outputs go to
I
8
Description
0
–I
H
X
X
H
X
X
L
–I
L
15
7
GND
GND
GND
CP
V
V
CP
NC
NC
4
CC
CC
1
2
NC
NC
I
I
I
I
I
I
I
5
11
13
n
1
3
5
7
9
Outputs
Outputs
O
O
input does
8
0
O
O
–O
H
–O
L
Z
H
Z
L
o
o
15
7
I
I
I
I
I
I
I
I
I
6
10
12
14
15
0
2
4
6
8