upd16879 Renesas Electronics Corporation., upd16879 Datasheet
upd16879
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upd16879 Summary of contents
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MONOLITHIC QUAD H BRIDGE DRIVER CIRCUIT The PD16879 is a monolithic quad H bridge driver IC that employs a CMOS control circuit and a MOSFET output circuit. Because it uses MOSFETs in its output stage, this driver IC consumes less ...
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ABSOLUTE MAXIMUM RATINGS (T When mounted on a glass epoxy board (100 mm Parameter Symbol Supply voltage Input voltage V IN Reference voltage V REF H bridge drive current I M(DC) I M(pulse) Power consumption P ...
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ELECTRICAL CHARACTERISTICS (Unless otherwise specified 250 mV, EVR = 100 mV (10000)) REF Parameter Symbol Off state V pin current I M MO(RESET) Operating state V pin current ...
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(VD-LATCH) LATCH SCLK t (SCLK-LATCH) Ignored because LATCH is at low level 50% LATCH D1 SDATA 50% SCLK t (SCLK-LATCH) Table 1. Chopping Frequency (3rd byte bit data, f Input data Chopping ...
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Table 2. Relation Between Rotation Angle, Phase Current, and Vector Quantity (Value of PD16879 for reference) STEP Rotation angle ( ) MIN 5.6 2.5 2 11.3 12.4 3 16.9 22.1 4 22.5 31.3 5 28.1 40.1 6 ...
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PIN CONFIGURATION RESET 38 LGND OSC 37 C OUT OSC OSC 36 FIL A IN SCLK 35 FIL B SDATA ...
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PIN FUNCTION Package: 38-pin plastic shrink SOP Pin Pin name 1 LGND 2 C OSC 3 FIL A 4 FIL B 5 FIL C 6 FIL REF ...
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I/O PIN EQUIVALENT CIRCUIT Pin name Equivalent circuit LATCH SDATA SCLK PAD OSC IN RESET V REFsel OSC OUT V EXT DD EXT PAD FIL A V FIL DD B FIL C FIL D ...
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OSC OSC V OUT RESET 1 OSC OSC + + – FILTER LGND 20 ...
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MHz TYP. OSC OSC RESET 2 5.5 V REGULATOR OSC BATTERY 4 ...
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SCLK SDATA 1st byte 13th byte (LSB) Data is held at rising edge SCLK Notes 1. ENABLE is set at the falling edge of FF1 when the level changes from low to high, and at the falling ...
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TIMING CHART (2) CLK (PULSE OUT) MOB (CW mode) H bridge , 1ch output Current direction Current direction bridge , 2ch output (Expanded view) CW mode CLK PULSE OUT ...
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STANDARD CHARACTERISTICS CURVES P vs. T characteristics T A 1.2 1.0 0.8 125 C/W 0.6 0.4 0.2 0 – Ambient temperature vs. V characteristics DD(RESET) DD 350 300 250 200 150 100 ...
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I vs. EVR characteristics mV 6 72.58 kHz S OSC 100 150 200 EVR setting voltage ...
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I/F CIRCUIT DATA CONFIGURATION (f Input data consists of serial data (8 bits Input serial data with the LSB first, from the first byte to 13th byte. [1st byte] Bit Data Function D7 8 bit data First point Note input ...
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Bit Data Function Enable Rotation D5 0 Not use D4 5 bit data channel input Current set Note Fixed ...
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Bit Data Function D7 16 bit data channel low-order Pulse Cycle D6 8 bit data D5 input Note D0 bit of 11th byte is LSB, and D7 bit of 12th byte is MSB. ...
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DATA CONFIGURATION Input data is composed of the serial data on 8 bits from the D0 bit (LSB) of the first byte. Therefore, the D7 bit of the 13th byte is the most significant bit (MSB). The establishment of the ...
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The 2nd byte specifies the delay between the first point wait time being cleared and the output pulse being generated. This time called the first point magnetize wait time, and the output pulse is generated from the point ...
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The test parameter is selected by bits D0 to D6. There are two EXT pins. EXT channel, and EXT indicates that of in Table 7. Table 7. Output Data of Test Parameter Bit Data ...
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Enable sets by D7 bit. D7 bit data is “0”: Output high impedance (but, internal counter increase) D7 bit data is “1”: Output conducts Rotation sets by D6 bit. D6 bit data is “0”: Forward turn (CW mode) D6 bit ...
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The 7th byte and 8th byte set the pulse cycle of the The pulse cycle is specified using 16 bits: bits D0 (least significant bit the 7th byte, and bits (most ...
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Table 13. Output Current Setting Reference Voltage Data ( channel data) EVR setting ...
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The 11th byte and 12th byte set the pulse cycle of the The pulse cycle is specified using 16 bits: bits D0 (least significant bit the 7th byte, and bits (most ...
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About Power Save Mode It is possible that circuit electric current is made small in the power saving (the following PS) mode. Data maintenance just before the PS mode and the maintenance of the phase position are done in the ...
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Data Update Timing The serial data of this product is set and update at the following timing. Table 16. Update Timing of The Data (1) Data First point wait time First point magnetize wait time EXP Chopping Power save The ...
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Initialization The IC operation can be initialized as follows: (1) Turns (2) Make RESET input low level signal. In initial mode, the operating status of the shown in Table 18. Table 18. Operations ...
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Hints on correct use (1) With this product, input the data for first point wait time and first point magnetize wait time. Because the serial data are set or updated by these wait times, if the first point wait time ...
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PACKAGE DRAWINGS 38-PIN PLASTIC SSOP (7.62 mm (300 NOTE Each lead centerline is located within 0. its true position (T.P.) at maximum material condition. 20 detail of lead end F 19 ...
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RECOMMENDED SOLDERING CONDITIONS Solder this product under the following recommended conditions. For soldering methods and conditions other than those recommended, consult NEC. For details of the recommended soldering conditions, refer to information document “Semiconductor Device Mounting Technology Manual”. Soldering Method ...
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NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation ...
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The information in this document is current as of May, 2000. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications ...