upd75112 Renesas Electronics Corporation., upd75112 Datasheet - Page 37

• Manufacturer Part Number: upd75112
• Description: 4-bit Single Chip-microcomputer
• Manufacturer: Renesas Electronics Corporation.

Subroutine
Stack Control
Interrupt
Control
Input/Output
CPU Control
Special
Instruction
* 1: MBE=0 or 1 and MBS=15 must be set for execution of IN/OUT instruction.
2: TBR and TCALL instructions are assembler pseudo-instructions for GETI instruction table definition.
Mnemonic
CALL
CALLF
RET
RETS
RETI
PUSH
POP
EI
DI
IN*1
OUT*1
HALT
STOP
NOP
SEL
GETI*2
!addr
!faddr
rp
BS
rp
BS
IE
IE
A, PORTn
XA, PORTn
PORTn, A
PORTn, XA
RBn
MBn
taddr
Operand
No. of Bytes
3
2
1
1
1
1
2
1
2
2
2
2
2
2
2
2
2
2
2
1
2
2
1
Machine Cycle
3+S
3
2
3
3
1
2
1
2
2
2
2
2
2
2
2
2
2
2
1
2
2
3
(SP-4)(SP-1)(SP-2) PC
(SP-3) MBE, RBE, PC
PC
(SP-4)(SP-1)(SP-2) PC
(SP-3) MBE, RBE, PC
PC
MBE, RBE, PC
PC
SP SP+4
MBE, RBE, PC
PC
SP SP+4, then skip unconditionally
PC
PC
PSW (SP+4)(SP+5), SP SP+6
(SP-1)(SP-2) rp, SP SP-2
(SP-1) MBS, (SP-2) RBS, SP SP-2
rp (SP-1)(SP), SP SP-2
MBS (SP+1), RBS (SP), SP SP+2
IME (IPS.3) 1
IE
IME (IPS.3) 0
IE
A PORTn
XA PORTn+1, PORTn (n=4, 6, 8, 12)
PORTn 4
PORTn+1, PORTn XA (n=4, 6, 8, 12)
Set HALT Mode (PCC.2 1)
Set STOP Mode (PCC.3 1)
No Operation
RBS n(n=0-3)
MBS n
,
TBR Instruction
PC
TCALL Instruction
(SP-4)(SP-1)(SP-2) PC
(SP-3) MBE, RBE, PC
PC
SP SP-4
When not TBR and TCALL instruc-
tions, (taddr) and (taddr+1) instruc-
tions are executed.
13-0
13-0
11-0
11-0
13, 12
11-0
13-0
13-0
1
addr, SP SP-4
(SP)(SP+3)(SP+2)
(SP)(SP+3)(SP+2)
(SP)(SP+3)(SP+2)
(SP+1)
(taddr)
(taddr)
faddr, SP SP-4
13, 12
13, 12
Operation
4-0
5-0
(n=0, 1, 15)
+(taddr+1)
+(taddr+1)
(n=0-9, 12-14)
(n=2-9, 12-14)
(SP+1)
(SP+1)
13, 12
13, 12
11-0
11-0
13, 12
11-0
Addressing Area
PD75112, 75116
*10
*6
*9
Unconditional
Depends on the
instruction
referred to.
Skip Condition
37