sc2441a Semtech Corporation, sc2441a Datasheet - Page 17

• Manufacturer Part Number: sc2441a
• Description: Sc2441a 1.8v To 20v Input 2-phase Synchronous Step-down Controllers With Step-up Converter
• Manufacturer: Semtech Corporation

Overview
The SC2441A is a constant-frequency switching regulator
capable of operating from 1.8V to 20V input. It consists of
two current-mode step-down switch-mode PWM controllers
driving all N-channel MOSFETs and an auxiliary step-up
current-mode converter with an integrated 0.6A power
switch. A local supply (>5V) can be generated from a low
voltage input (3.3V, 2.5V or 1.8V) to provide sufficient gate
drives for the step-down converters.
The two step-down channels of the SC2441A operate at
180 degrees out of phase from each other. Input currents
are interleaved in a two-phase converter so input ripple
current is lower and lower input capacitance can be used
for filtering.
The step-down controllers of the SC2441A operate in
synchronous continuous-conduction mode. They can
function either as two independent step-down controllers
producing two separate outputs or as a dual-phase single-
output controller by tying the FB2 pin to V
single output mode, the channel 1 error amplifier controls
both channels and the channel 2 error amplifier is
disabled. Soft-start and overload hiccup of both channels
are also controlled by channel 1. In Figure 2 the output
SEL of the comparator A1 determines which error amplifier
outputs and fault signals are routed to channel 2. The
minimum required FB2 voltage for single output mode is
1.55V.
Phase-Locked Loop and Synchronization
The SC2441A utilizes a phase-locked oscillator (Figure 5)
for clock generation and external synchronization. The
advantages of using a phase-locked loop (PLL) are: (i) when
the step-down channels are synchronized, the auxiliary step-
up regulator in the SC2441A can be made to run at twice
the external clock frequency to reduce component size and
(ii) two or more SC2441A can be daisy chained using the
clock output (pin 28) and interleaved with programmable
phase shift. Each step-down controller within a SC2441A
operates at 180 degrees out of phase from the other step-
down controller. The switching frequency of the step-down
controllers can be set with an external resistor ROSC. The
boost regulator and the step-down controllers are capable
of operating up to 2 MHz and 1 MHz respectively. It is
POWER MANAGEMENT
Operation
2006 Semtech Corp.
IN
(Figure 2). In
17
necessary to consider the operating duty-ratio range
before deciding the switching frequency. See Applications
Information section for more details.
Consider the detailed block diagram of the PLL in Figure
5. The phase/frequency detector compares the buffered
external clock XCLK with the
flop. If the rising edge of XCLK leads that of
will go high between the two corresponding rising edges.
Switch S
and the voltage at the PLLF pin increases. This in turn
causes the current output of the voltage to current converter
(V/I) and the switching frequency of the current-controlled
oscillator (CCO) to increase. If
Q
edge of XCLK. Switch S
the loop filter and the PLLF voltage falls. The switching
frequency of the current-controlled oscillator (CCO)
decreases. When the PLL is in lock, the rising edges of
XCLK and
few gate delays. The PLLF stabilizes to a constant DC
voltage and the CCO runs at the same frequency as the
external clock.
In the absence of an external clock, S
PLL loop filter is continuously discharged. Not shown in
Figure 5 is an internal PLLF lower clamp circuit that limits
the minimum voltage at the PLLF pin to 0.17V. This sets
the lowest operating frequency and thus the lower bound
of the PLL lock-range. The V/I in Figure 5 is shown with
two non-inverting inputs. The lower voltage non-inverting
input takes control of the V/I. If the PLLF pin is tied to VIN
(>1.8V) through a current-limiting resistor, then the 0.4V
input of the V/I will predominate. The 0.4V input therefore
sets the upper excursion limit of the V/I and the maximum
operating frequency of the PLL at a given ROSC. The
maximum PLL frequency to the minimum locking frequency
ratio is about 2. When the SC2441A is not synchronized
externally, the PLLF pin should be tied high through a
resistor. The CCO will then run at its maximum frequency.
When two SC2441As are used in a master-slave
configuration, the PLLF pin of the master SC2441A is tied
high and its free running frequency is set with the resistor
ROSC. CKOUT of the master is then tied to the
input of the slave SC2441A. The free running and the
D
will go high from the rising edge of
1
is closed, charge is delivered to the loop filter
Q are aligned. Q
T
2
is closed, charge is drawn from
U
and Q
Q output of the toggle flip-
Q rises before XCLK, then
T
T
D
will go high for only a
2
SC2441A
is closed and the
Q
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T
SYNC/
Q , then Q
to the rising
T
SHDN
U