st72321j STMicroelectronics, st72321j Datasheet - Page 121

• Manufacturer Part Number: st72321j
• Description: 8-bit Mcu With Nested Interrupts, Flash, 10-bit Adc, 5 Timers, Spi, Sci, I2c Interface
• Manufacturer: STMicroelectronics

I
I
Read / Write
Reset Value: 0000 0000 (00h)
Bit 7 = FM/SM Fast/Standard I
This bit is set and cleared by software. It is not
cleared when the interface is disabled (PE=0).
0: Standard I
1: Fast I
Bit 6:0 = CC[6:0] 7-bit clock divider.
These bits select the speed of the bus (F
pending on the I
when the interface is disabled (PE=0).
– Standard mode (FM/SM=0): F
– Fast mode (FM/SM=1): F
Note: The programmed F
SCL and SDA lines.
FM/SM
2
2
C BUS INTERFACE (Cont’d)
C CLOCK CONTROL REGISTER (CCR)
7
F
F
CC6
SCL
SCL
2
C mode
= F
= F
2
CC5
C mode
CPU
CPU
2
C mode. They are not cleared
/(2x([CC6..CC0]+2))
/(3x([CC6..CC0]+2))
CC4
SCL
CC3
SCL
assumes no load on
2
C mode.
> 100kHz
SCL
CC2
<= 100kHz
CC1
SCL
CC0
) de-
0
I
Read / Write
Reset Value: 0000 0000 (00h)
Bit 7:0 = D[7:0] 8-bit Data Register.
These bits contain the byte to be received or trans-
mitted on the bus.
– Transmitter mode: Byte transmission start auto-
– Receiver mode: the first data byte is received au-
2
C DATA REGISTER (DR)
matically when the software writes in the DR reg-
ister.
tomatically in the DR register using the least sig-
nificant bit of the address.
Then, the following data bytes are received one
by one after reading the DR register.
D7
7
D6
D5
D4
D3
D2
ST72321J
D1
121/179
D0
0