st72324bk STMicroelectronics, st72324bk Datasheet - Page 91

• Manufacturer Part Number: st72324bk
• Description: 3 V/5 V Range 8-bit Mcu With 4/8 Kbyte Rom, 10-bit Adc, Four Timers And Spi
• Manufacturer: STMicroelectronics

ST72323 ST72323L
Note:
Caution:
Figure 46. Generic SS timing diagram
Figure 47. Hardware/software slave select management
Master mode operation
In master mode, the serial clock is output on the SCK pin. The clock frequency, polarity and
phase are configured by software (refer to the description of the SPICSR register).
The idle state of SCK must correspond to the polarity selected in the SPICSR register (by
pulling up SCK if CPOL=1 or pulling down SCK if CPOL=0).
How to operate the SPI in master mode
To operate the SPI in master mode, perform the following steps in order:
1.
2.
3.
if the SPICSR register is not written first, the SPICR register setting (MSTR bit) may be not
taken into account.
The transmit sequence begins when software writes a byte in the SPIDR register.
MOSI/MISO
Master SS
Slave SS
(if CPHA=0)
Write to the SPICR register:
–
–
Write to the SPICSR register:
–
Write to the SPICR register:
–
Select the clock frequency by configuring the SPR[2:0] bits.
Select the clock polarity and clock phase by configuring the CPOL and CPHA bits.
Figure 48
the same CPOL and CPHA settings as the master.
Either set the SSM bit and set the SSI bit or clear the SSM bit and tie the SS pin
high for the complete byte transmit sequence.
Set the MSTR and SPE bits. Note that the MSTR and SPE bits remain set only if
SS is high).
shows the four possible configurations. Note that the slave must have
SS external pin
SSI bit
Byte 1
SSM bit
1
0
Byte 2
SS internal
Byte 3
On-chip peripherals
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