st72324bk STMicroelectronics, st72324bk Datasheet - Page 92

• Manufacturer Part Number: st72324bk
• Description: 3 V/5 V Range 8-bit Mcu With 4/8 Kbyte Rom, 10-bit Adc, Four Timers And Spi
• Manufacturer: STMicroelectronics

On-chip peripherals
Note:
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Master mode transmit sequence
When software writes to the SPIDR register, the data byte is loaded into the 8-bit shift
register and then shifted out serially to the MOSI pin most significant bit first.
When data transfer is complete:
Clearing the SPIF bit is performed by the following software sequence:
1.
2.
While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR
register is read.
Slave mode operation
In slave mode, the serial clock is received on the SCK pin from the master device.
To operate the SPI in slave mode:
1.
2.
Slave mode transmit sequence
When software writes to the SPIDR register, the data byte is loaded into the 8-bit shift
register and then shifted out serially to the MISO pin most significant bit first.
The transmit sequence begins when the slave device receives the clock signal and the most
significant bit of the data on its MOSI pin.
When data transfer is complete:
Clearing the SPIF bit is performed by the following software sequence:
1.
2.
–
–
An access to the SPICSR register while the SPIF bit is set
A read to the SPIDR register.
Write to the SPICSR register to perform the following actions:
–
–
Write to the SPICR register to clear the MSTR bit and set the SPE bit to enable the SPI
I/O functions.
–
–
An access to the SPICSR register while the SPIF bit is set.
A write or a read to the SPIDR register.
The SPIF bit is set by hardware
An interrupt request is generated if the SPIE bit is set and the interrupt mask in the
CCR register is cleared.
Select the clock polarity and clock phase by configuring the CPOL and CPHA bits
(see
Note that the slave must have the same CPOL and CPHA settings as the master.
Manage the SS pin as described in
be held low continuously. If CPHA=0 SS must be held low during byte
transmission and pulled up between each byte to let the slave write in the shift
register.
The SPIF bit is set by hardware
An interrupt request is generated if SPIE bit is set and interrupt mask in the CCR
register is cleared.
Figure
48).
Section
and
Figure
46. If CPHA=1 SS must
ST72323 ST72323L