st72324bk STMicroelectronics, st72324bk Datasheet - Page 99

• Manufacturer Part Number: st72324bk
• Description: 3 V/5 V Range 8-bit Mcu With 4/8 Kbyte Rom, 10-bit Adc, Four Timers And Spi
• Manufacturer: STMicroelectronics

ST72323 ST72323L
Note:
Control/status register (SPICSR)
Reset value: 0000 0000 (00h)
Bit 7 = SPIF Serial Peripheral Data Transfer Flag (read only).
While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR
register is read.
Bit 6 = WCOL Write Collision status (read only).
Bit 5 = OVR SPI Overrun error (read only).
Bit 4 = MODF Mode Fault flag (read only).
Bit 3 = Reserved, must be kept cleared.
Bit 2 = SOD SPI Output Disable.
SPIF
This bit is set by hardware when a transfer has been completed. An interrupt is
generated if SPIE=1 in the SPICR register. It is cleared by a software sequence (an
access to the SPICSR register followed by a write or a read to the SPIDR register).
0: Data transfer is in progress or the flag has been cleared.
1: Data transfer between the device and an external device has been completed.
This bit is set by hardware when a write to the SPIDR register is done during a transmit
sequence. It is cleared by a software sequence (see
0: No write collision occurred
1: A write collision has been detected
This bit is set by hardware when the byte currently being received in the shift register is
ready to be transferred into the SPIDR register while SPIF = 1 (See
interrupt is generated if SPIE = 1 in SPICR register. The OVR bit is cleared by software
reading the SPICSR register.
0: No overrun error
1: Overrun error detected
This bit is set by hardware when the SS pin is pulled low in master mode (see
Master mode fault
SPICSR register. This bit is cleared by a software sequence (An access to the SPICR
register while MODF=1 followed by a write to the SPICR register).
0: No master mode fault detected
1: A fault in master mode has been detected
This bit is set and cleared by software. When set, it disables the alternate function of
the SPI output (MOSI in master mode / MISO in slave mode)
0: SPI output enabled (if SPE=1)
1: SPI output disabled
7
WCOL
Read only
(MODF)). An SPI interrupt can be generated if SPIE=1 in the
OVR
MODF
Reserved
-
Figure
SOD
49).
On-chip peripherals
Read/write
Section
SSM
). An
Section :
SSI
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