sm59d03g2c25 SyncMOS Technologies,Inc, sm59d03g2c25 Datasheet

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... Product List SM59D03G2L25, 25MHz 8KB+ internal Flash MCU SM59D03G2C25, 25MHz 8KB+ internal Flash MCU Description The SM59D03G2 series product is an 8-bit single chip macro-controller with 8K bytes Flash & 1K byte RAM embedded derivative of the 8052 micro-controller family with a fully compatible instruction sets. ...

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Pin Configuration T2/P1.0 T2EX/P1.1 CCCI/P1.2 CC0/P1.3 CC1/P1.4 CC2/P1.5 CC3/P1.6 CC4/P1.7 RESET RXD/P3.0 TXD/P3.1 INT0/P3.2 INT1/P3.3 T0/P3.4 T1/P3.5 WR/P3.6 RD/P3.7 XTAL2 XTAL1 Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M030 ...

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CC2/P1.5 CC3/P1.6 CC4/P1.7 RESET RXD/P3.0 P4.3 TXD/P3.1 INT0/P3.2 INT1/P3.3 T0/P3.4 T1/P3.5 Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M030 ...

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AD3/P0.3 35 AD2/P0.2 36 AD1/P0.1 37 AD0/P0.0 38 VDD 39 P4.2 40 T2/P1.0 41 T2EX/P1.1 42 CCCI/P1.2 43 CC0/P1.3 44 CC1/P1.4 Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M030 8-Bits Micro-controller ...

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Block Diagram Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M030 8-Bits Micro-controller 8KB+ ISP Flash & 1KB RAM embedded 5 Ver.C SM59D03G2 07/2009 SM59D03G2 ...

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Pin Description 40L 44L 44L PDIP QFP PLCC Symbol Pin# Pin# Pin P10/T2/EEI0/ICP_CLK P11/T2EX/EEI1/ICP_TRIG P12/CCCI/EEI2 /ICP_DATA P13/CC0/EEI3 P14/CC1/EEI4 P15/CC2/EEI5 ...

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Special Function Register (SFR) Address 80h to FFh is the location of SM59D03G2 special function register (SFR). These locations must be accessed by direct addressing mode only. The following table gives the SFRs, part of them are identically located and ...

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Register Location TH1 8Dh WDTC 8Eh WDTK 8Fh P1 90h CC2DH 91h CC2DL 92h CC3DH 93h CC3DL 94h CC4DH 95h CC4DL 96h SCON 98h SBUF 99h PCACH 9Ah PCACL 9Bh CC0DH 9Ch CC0DL 9Dh CC1DH 9Eh CC1DL 9Fh P2 A0h ...

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Register Location PSW D0h P4 D8h ACC E0h B F0h ISPFAH F4h ISPFAL F5h ISPFD F6h ISPC F7h KBLS FDh KBE FEh KBF FFh Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M030 ...

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Function Description 1 General Features SM59D03G2 is an 8-bit micro-controller. All of its functions and the detailed meanings of SFR will be given in the following sections. 1.1 Embedded Flash The program can be loaded into the embedded 8K bytes ...

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Selection The conventional 52-series MCUs are 12T, i.e., 12 oscillator clocks per one machine cycle. If the machine cycle is changed to 6 clocks, then this 6T mode will double the running speed of 12T’s with the same ...

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Instruction set The SM59D03G2 uses the powerful 80C51 instruction set. It consists of 49 single-byte, 42 two-byte and 15 three-byte instructions. Among them, 63 instructions are executed in 1 machine-cycle, 46 instructions in 2 machine-cycles and 2 instructions in ...

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Data Transfers Instructions MOV A, Rn MOV A, direct MOV A, @Ri MOV A, #data MOV Rn, A MOV Rn, direct MOV Rn, #data MOV direct, A MOV direct, Rn MOV direct, direct MOV direct, @Ri MOV direct, #data MOV ...

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Memory Structure The SM59D03G2 manipulates operands in three memory spaces. They are (1) 256 bytes standard RAM, (2) 768 bytes auxiliary RAM，and (3) 8K bytes embedded Flash as program memory. 3.1 Program Memory As described in Section 1, the ...

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The SM59D03G2 provides code protect function on the writer. The user can select protect or unprotect by writer. If protection is selected, users can’t read the program from the writer. When the user runs in the external program mode (EA ...

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Data Memory - Lower 128 byte ($00h to $7Fh) Data Memory 00h to FFh is the same as defined in 8052. The address 00h to 7Fh can be accessed by both direct and indirect addressing modes. Address 00h to ...

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CPU Engine The SM59D03G2 CPU engine allows fetching instructions from the program memory, and accessing data with RAM or SFR. Here the SFR in the CPU engine is explained. Mnemonic Description ACC Accumulator B B register Program status PSW ...

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CY: Carry flag. AC: Auxiliary Carry flag for BCD operations. F0: General purpose Flag 0 available for user. RS[1:0]: Register bank select, used to select working register bank. RS[1: OV: Overflow flag. F1: General purpose Flag ...

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Data Pointer 1 The dual data pointer accelerates the moving of block data. The standard DPTR is a 16-bit register that is used to address external memory or peripherals. In the SM59D03G2, the standard data pointer is called DPTR，the ...

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Port 0 – Port 4 Port 0 ~ Port 4 are the general purpose IO of this controller. Port 4[3:0] is available with 44-pin PLCC or QFP package only, not for 40-pin package. Most of the ports are multiplexed ...

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Timer 0 and Timer 1 These timer and counter functions are presented in the same module. The “timer” or “counter” function is selected by the control bits SFR TMOD. Timer 0 and Timer 1 have four ...

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Mode 1 Mode 1 is the same as Mode 0, except that the timer register runs with all 16 bits. INT 1 6.3 Mode 2 For Timer 1, Mode 2 configures the timer register as an 8-bit counter (TL1) ...

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Mode 3 Timer 1 in Mode 3 simply holds its count. The effect is the same as setting TR1 = 0. Timer 0 in Mode 3 takes TL0 and TH0 as two separate counters. TL0 uses the Timer 0 ...

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Timer/Counter Mode Control register (TMOD) Mnemonic: TMOD 7 6 GATE C/ T Timer 1 GATE: If set, enables external gate control (pin INT0 or INT1 for Counter respectively). When INT0 or INT1 is high, and TRx ...

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Timer/Counter Control register (TCON) Mnemonic: TCON 7 6 TF1 TR1 TF1: Timer 1 overflow flag set by hardware when Timer 1 overflows. This flag can be cleared by software and is automatically cleared when interrupt is processed. TR1: Timer ...

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Timer 2 Timer 16-bit timer/counter which can operate either as a timer or an event counter. This is selectable by bit the SFR T2CON. It has three operating modes: capture, auto-reload (up T ...

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Auto-reload (Up or Down Counter) Timer 2 can be programmed to count up or down when configured in its 16-bit auto-reload mode. This feature is invoked by a bit named DCEN (Down Counter Enable) located in the SFR T2MOD. ...

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Figure 7-2：Timer 2 in auto reload mode (DCEN=0) Figure 7-3： Timer 2 in auto reload mode (DCEN=1) 7.3 Programmable clock out A 50% duty cycle clock can be programmed to come out on P1.0. This pin, besides begin a regular ...

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Clock-Out Frequency = × the clock-out mode, Timer 2 roll-overs will not generate an interrupt. This is similar to when Timer 2 is used as a baud-rate generator possible to use Timer baud-rate ...

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Mnemonic: T2CON 7 6 TF2 EXF2 RCLK TF2: Timer 2 overflow flag is set by a Timer 2 overflow and must be cleared by software. TF2 will not be set when either RCLK = 1 or TCLK = 1. EXF2: ...

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Watchdog timer The watchdog timer is an 8-bit counter that is incremented once every WDTCLK clock cycle. After an external reset, the watchdog timer is disabled and all registers are set to zero. When SM59D03G2 is reset, it will ...

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Mnemonic: WDTK 7 6 WDTK: Watchdog timer refresh key. A programmer must set it to 1Eh first, then E1h next. After these, the above SFR WDTC can be set. Specifications subject to change without notice contact your sales representatives for ...

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ISP (In-System Programming) The SM59D03G2 can perform ISP or In-Application Programming (IAP) function by putting the ISP service code into the assigned ISP code area as shown in Table 9-1. One page of Flash memory is 512bytes. Lock-bit number ...

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SFR description Description Mnemonic ISP control ISPC register ISP Flash ISPFAH address high byte ISP Flash ISPFAL address low byte ISPFD ISP Flash data Mnemonic: ISPFAH 7 6 Mnemonic: ISPFAL 7 6 ISPFA[15:0]: The ISPFAH and ISPFAL provide the ...

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Ex: Open ISP function: MOV ISPFD,#055h MOV ISPFD,#0AAh MOV ISPFD,#055h Any attempt to set START bit will not be allowed without procedure above. After the START bit set to 1, the SM59D03G2 hardware circuit will latch the address and data ...

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Serial interface (UART) The UART serial port is full duplex, meaning it can transmit and receive simultaneously also receive-buffered, meaning it can commence reception of a second byte before a previously received byte has been read from ...

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When the master processor wants to transmit a block of data to one of several slaves, it first sends out an address byte which identifies the target slave. An address byte differs from a data byte in th that the ...

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Using Timer 2 to Generate Baud Rates. In the SM59D03G2, Timer 2 is selected as the baud rate generator by setting TCLK and/or RCLK in T2CON. Note then the baud rates for transmit and receive can be simultaneously different. ...

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Figure 10-1 Timer 2 in Baud Rate Generator Mode 10.5 SFR description Mnemonic Description PCON Power Control Serial port 0 SCON control register Serila port 0 data SBUF buffer Mnemonic: PCON 7 6 SMOD - SMOD: This bit set to ...

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SM0,SM1 SM0, SM1 specify the serial port mode as follows (Fosc is the system frequency) : SM0 SM2 Enables the multiprocessor communication feature in Modes 2 and 3. In Mode SM2 is ...

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Programmable Counter Array (PCA) The PCA provides more timing capabilities with less CPU intervention than the standard timer/counters. The PCA consists of a dedicated counter which serves as the time base for an array of five compare/capture modules. Its ...

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Table 11-1 PCA clock sample period example Machine Fcry CCCLK[1:0] cycle (MHz 12T 16 12T 16 12T 16 6T/12T Note: Besides PCA counter increment from External clock input, Sample period(us ...

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Fig 11-2: PCA capture mode with positive edge 11.2.2 Negative edge capture mode: The external input pins CC0 through CC4 are sampled for a 1-to 0 transition. When a negative edge transition is detected, hardware loads the 16-bit value of ...

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Fig 11-4: PCA capture mode with both negative and positive edge 11.2.4 Timer mode: In the Timer mode. When the PCA counter rolls over, the CCnIF bit will be set which can then generate an interrupt if CCnIE is enabled ...

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CCnD[15:0] PCA 16 bit 16 bit comparator counter 11.2.6 8-bit PWM: Any or all of the five PCA modules can be programmed Pulse Width Modulator (PWM). The PWM output can be used to convert digital data to ...

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PCA SFR description Description Mnemonic PCA control PCAC1 register 1 PCA control PCAC2 register 2 PCA counter high PCAH byte PCA counter low PCAL byte CC0 control CC0CON register CC0 data high CC0DH byte CC0 data low CC0DL byte ...

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PCA Control register 1 Mnemonic: PCAC1 7 6 CCR CIDL R/W R/W CCR: PCA Counter Run control bit. Set by software to turn the PCA counter on. Must be cleared by software to turn the PCA counter off. CIDL: ...

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Compare/Capture channel 0 control register Mnemonic: CC0CON CC0MOD[2:0] Compare/Capture channel 0 modes select. CC0MOD[2:0] 000 001 010 011 100 101 110 111 TOG0: CC0 toggle register. 11.3.5 CC0 Data register Mnemonic: CC0DH 7 ...

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Compare/Capture channel 1 control register Mnemonic: CC1CON CC1MOD[2:0] Compare/Capture channel 1 modes select. CC1MOD[2:0] 000 001 010 011 100 101 110 111 TOG1: CC1 toggle register. 11.3.7 CC1 Data register Mnemonic: CC1DH 7 ...

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Compare/Capture channel 2 control register Mnemonic: CC2CON CC2MOD[2:0] Compare/Capture channel 2 modes select. CC2MOD[2:0] 000 001 010 011 100 101 110 111 TOG2: CC2 toggle register. 11.3.9 CC2 Data register Mnemonic: CC2DH 7 ...

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Compare/Capture channel 3 control register Mnemonic: CC3CON CC3MOD[2:0] Compare/Capture channel 3 modes select. CC3MOD[2:0] 000 001 010 011 100 101 110 111 TOG3: CC3 toggle register. 11.3.11 CC3 Data register Mnemonic: CC3DH 7 ...

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Compare/Capture channel 4 control register Mnemonic: CC4CON CC4MOD[2:0] Compare/Capture channel 4 modes select. CC4MOD[2:0] 000 001 010 011 100 101 110 111 TOG4: CC4 toggle register. 11.3.13 CC4 Data register Mnemonic: CC4DH 7 ...

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Expanded External Interrupt (EEI) interface SM59D03G2 implements an EEI interface allowing the connection of an 8xn matrix keyboard based on 8 inputs with programmable interrupt capability for either high or low levels. These inputs are available as ...

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EEI SFR description Description Mnemonic EEI level Selector KBLS register EEI Input Enable KBE register KBF EEI Flag register 12.1.1 EEI level selector register Mnemonic: KBLS 7 6 KBLS7 KBLS6 R/W R/W KBLS7: EEI line 7 level selection bit ...

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EEI input enable register Mnemonic: KBE 7 6 KBE7 KBE6 KBE5 R/W R/W R/W KBE7: EEI line 7 Enable bit Cleared to enable standard I/O pin. Set to enable KBE.7 bit in KBE register to generate an EEI interrupt ...

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EEI flag register Mnemonic: KBF 7 6 KBF7 KBF6 KBF5 R R KBF7: EEI line 7 flag Set by hardware when the port line 7 detects a programmed level. It generates a EEI interrupt request if the KBE.7 bit ...

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Interrupts SM59D03G2 has a total of 8 interrupt vectors, they include two external interrupts, three timer interrupts, one serial port interrupts, EEI interrupts, and a PCA interrupt. Each of the interrupt sources can be individually enabled or disabled by ...

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Mnemonic: IE1 EPCA: PCA interrupt enable bit. KBD: EEI interrupt enable bit. Cleared to disable EEI interrupt. Set to enable EEI interrupt. Mnemonic PT2: Timer 2 interrupt priority bit. PT2 = ...

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Power Management 14.1 Idle Mode The user can enter the idle mode by setting the IDLE bit in the PCON register. In the idle mode, the internal clock to the CPU part is stopped but the clock still remains ...

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Operating Conditions Symbol Description TA Operating temperature VCC5 Supply voltage Fosc 25 Oscillator Frequency DC Characteristics (TA = -40 degree degree C, Vcc = 5V) Symbol Parameter VIL1 Input Low Voltage VIL2 Input Low Voltage VIH1 Input ...

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AC Characteristics (16/25 MHz, operating conditions; CL for Port 0, ALE and PSEN Outputs=150pF; CL for all Other Output=80pF) Symbol Parameter T LHLL ALE pulse width T AVLL Address Valid to ALE low T LLAX Address Hold after ALE low ...

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Application Reference Valid for SM59D03G2 X'tal 2MHz 6MHz 10MHz X'tal 16MHz 25MHz NOTE: Oscillation circuit may ...

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Data Memory Read Cycle Timing Program Memory Read Cycle Timing Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M030 8-Bits Micro-controller 8KB+ ISP Flash & 1KB RAM embedded 63 Ver.C SM59D03G2 07/2009 SM59D03G2 ...

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Data Memory Write Cycle Timing I/O Ports Timing Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M030 8-Bits Micro-controller 8KB+ ISP Flash & 1KB RAM embedded 64 Ver.C SM59D03G2 07/2009 SM59D03G2 ...

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Timing Critical, Requirement of External Clock Tm.I External Program Memory Read Cycle Tm.II External Data Memory Read Cycle Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M030 8-Bits Micro-controller 8KB+ ISP Flash & ...

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Tm.III External Data Memory Write Cycle Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M030 8-Bits Micro-controller 8KB+ ISP Flash & 1KB RAM embedded 66 Ver.C SM59D03G2 07/2009 SM59D03G2 ...

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Company Advantech 7F, No.98, Ming-Chung Rd., Shin-Tien City, Taipei, Taiwan, ROC Web site: http://www.aec.com.tw Hi-Lo 4F.,No.18,Lane 79,Rueiguang Rd.,Neihu,Taipei,Taiwan R.O.C. Web site: http://www.hilosystems.com.tw Xeltek Electronic Co., Ltd Bldg 6-31 Meizhiguo garden, #2 Jiangjun Ave., Jiangning, Nanjing, China 211100 Web site: http://www.xeltek-cn.com ...