fm3316 Ramtron Corporation, fm3316 Datasheet - Page 19

• Manufacturer Part Number: fm3316
• Description: 3v Integrated Processor Companion With Memory
• Manufacturer: Ramtron Corporation

Command Structure
There are eight commands called op-codes that can
be issued by the bus master to the FM33xx. They are
listed in the table below. These op-codes control the
functions performed by the memory and Processor
Companion. They can be divided into three
categories. First, there are commands that have no
subsequent operations. They perform a single
function, such as, enabling a write operation. Second
are commands followed by one data byte, either in or
out. They operate on the Status Register. The third
group includes commands for memory and Processor
Companion transactions followed by address and one
or more bytes of data.
Table 4. Op-code Commands
WREN – Set Write Enable Latch
The FM33xx will power up with writes disabled. The
WREN command must be issued prior to any write
Rev. 1.1
Dec. 2007
Name
WREN
WRDI
RDSR
WRSR
READ
WRITE
RDPC
WRPC
Description
Set Write Enable Latch
Write Disable
Read Status Register
Write Status Register
Read Memory Data
Write Memory Data
Read Proc. Companion
Write Proc. Companion
SCK
SCK
SO
SO
CS
CS
SI
SI
0
0
0
0
Figure 13. WREN Bus Configuration
0
0
Figure 14. WRDI Bus Configuration
Op-code
0000 0110b
0000 0100b
0000 0101b
0000 0001b
0000 0011b
0000 0010b
0001 0011b
0001 0010b
1
1
0
0
2
2
0
0
Hi-Z
Hi-Z
3
3
0
0
4
4
operation. Sending the WREN op-code will allow
the user to issue subsequent op-codes for write
operations. These include writing the Status
Register, writing the Processor Companion, and
writing the memory.
Sending the WREN op-code causes the internal
Write Enable Latch to be set. A flag bit in the Status
Register, called WEL, indicates the state of the
latch. WEL=1 indicates that writes are permitted.
Attempting to write the WEL bit in the Status
Register has no effect on the state of this bit. The
WEL bit will automatically be cleared on the rising
edge of /CS following a WRDI, WRSR, WRPC, or
WRITE op-code. No other op-code affects the state
of the WEL bit. This prevents further writes to the
Status Register, F-RAM memory, or the companion
register space without another WREN command.
Figure 13 below illustrates the WREN command
bus configuration.
WRDI – Write Disable
The WRDI command disables all write activity by
clearing the Write Enable Latch. The user can verify
that writes are disabled by reading the WEL bit in
the Status Register and verifying that WEL=0.
Figure 14 illustrates the WRDI command bus
configuration.
FM33256/FM3316 SPI Companion w/ FRAM
5
1
5
1
1
6
0
6
7
7
0
0
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