fm3316 Ramtron Corporation, fm3316 Datasheet - Page 22

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fm3316

Manufacturer Part Number
fm3316
Description
3v Integrated Processor Companion With Memory
Manufacturer
Ramtron Corporation
Datasheet

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After the op-code and address are issued, the device
drives out the read data on the next 8 clocks. The SI
input is ignored during read data bytes. Subsequent
bytes are data bytes, which are read out sequentially.
Addresses are incremented internally as long as the
bus master continues to issue clocks and /CS is low.
Addressing F-RAM Array in the FM33xx Family
The FM33xx devices include 256Kb and 16Kb memory densities. The following 2-byte address field is shown for
each density.
Table 7. Two-Byte Memory Address
Rev. 1.1
Dec. 2007
SCK
SCK
SO
CS
CS
SO
SI
Part #
SI
FM33256
FM3316
0
0
0
0
0
0
1
1
0
0
2
2
Op-code
Op-code
Hi-Z
Hi-Z
0
0
x
x
3
3
0
0
4
4
A14
x
0
0
5
5
A13
1
1
x
6
6
1
st
0
1
Address Byte
7
7
A12
x
MSB
MSB
X
X
0
0
Figure 19. Memory Write
Figure 20. Memory Read
A11
14
14
1
1
x
13
13
2
2
16-bit Address
16-bit Address
A10
A10
12
12
3
3
11
11
A9
A9
4
4
If the last address is reached (e.g. 7FFFh on the
FM33256), the counter will roll over to 0000h. Data
is read MSB first. The rising edge of /CS terminates a
READ operation.
Figure 20.
A8
A8
1
1
6
6
FM33256/FM3316 SPI Companion w/ FRAM
LSB
LSB
0
0
7
7
A7
A7
MSB
MSB
7
7
0
0
A6
A6
1
6
1
6
2
5
2
5
A5
A5
A read operation is shown in
2
Data Out
nd
Data In
4
3
3
4
Address Byte
A4
A4
4
3
4
3
A3
A3
5
2
5
2
A2
A2
6
1
6
1
LSB
LSB
7
0
7
0
A1
A1
Page 22 of 28
A0
A0
0
0
7
7

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