t71l6808a TM Technology Inc., t71l6808a Datasheet - Page 4

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t71l6808a

Manufacturer Part Number
t71l6808a
Description
Octal 10/100 Switch With Embedded Memory
Manufacturer
TM Technology Inc.
Datasheet
tm
TE
CH
Preliminary T71L6808A
Block Diagram
Functional Description
Reset
After power on reset, the T71L6808A will determine some features from ENFCTRL and
ENBKPRS pins, auto-load the content of 24LC02 serial EEPROM, and write abilities to
connected PHY management registers via MDC/MDIO.
RMII Interface
The T71L6808A provides 10/100 Mbps low pin count RMII interface for use between PHY and
T71L6808A. The RMII is capable of supporting 10Mbps and 100Mbps data rates. A single clock
reference, 50MHz, sourced from an external clock input is used for receive and transmit. It also
provides independent 2 bit wide (di-bit) transmit and receive data paths. As the REFCLK is 10
times the data rate in 10Mbps mode each data di-bit must be output on TXD[1:0] and input on
RXD[1:0] for ten consecutive REFCLK cycles.
Taiwan Memory Technology, Inc. reserves the right
P. 4
Publication Date:May. 2001
to change products or specifications without notice.
Revision:0.A

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