isl12022m Intersil Corporation, isl12022m Datasheet - Page 13

• Manufacturer Part Number: isl12022m
• Description: Real Time Clock With Embedded Crystal, ??5ppm Accuracy
• Manufacturer: Intersil Corporation

ADDR. SECTION
Real Time Clock Registers
Addresses [00h to 06h]
RTC REGISTERS (SC, MN, HR, DT, MO, YR, DW)
These registers depict BCD representations of the time. As
such, SC (Seconds) and MN (Minutes) range from 0 to 59,
HR (Hour) can either be a 12-hour or 24-hour mode, DT
(Date) is 1 to 31, MO (Month) is 1 to 12, YR (Year) is 0 to 99,
and DW (Day of the Week) is 0 to 6.
The DW register provides a Day of the Week status and uses
three bits (DW2 to DW0) to represent the seven days of the
week. The counter advances in the cycle 0-1-2-3-4-5-6-0-1-
2-… The assignment of a numerical value to a specific day
of the week is arbitrary and may be decided by the system
software designer. The default value is defined as “0”.
24 HOUR TIME
If the MIL bit of the HR register is “1”, the RTC uses a
24-hour format. If the MIL bit is “0”, the RTC uses a 12-hour
format and HR21 bit functions as an AM/PM indicator with a
“1” representing PM. The clock defaults to 12-hour format
time with HR21 = “0”.
LEAP YEARS
Leap years add the day February 29 and are defined as those
years that are divisible by 4. Years divisible by 100 are not leap
years, unless they are also divisible by 400. This means that
the year 2000 is a leap year and the year 2100 is not. The
ISL12022M does not correct for the leap year in the year 2100.
Control and Status Registers (CSR)
Addresses [07h to 0Fh]
The Control and Status Registers consist of the Status
Register, Interrupt and Alarm Register, Analog Trimming and
Digital Trimming Registers.
STATUS REGISTER (SR)
The Status Register is located in the memory map at
address 07h. This is a volatile register that provides either
control or status of RTC failure (RTCF), Battery Level
Monitor (LBAT85, LBAT75), alarm trigger, Daylight Saving
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
ALPHAH
NPPM
GPM
XT0
TABLE 1. REGISTER MEMORY MAP (YELLOW SHADING INDICATES READ-ONLY BITS) (Continued)
ALPHAH
NAME
NPPMH
NPPML
GPM1
GPM2
REG
XT0
13
NPPM7
GPM17
GPM27
D
D
0
7
ALP_H6
NPPM6
GPM16
GPM26
D
6
0
ALP_H5
NPPM5
GPM25
GPM15
D
5
0
ISL12022M
ALP_H4
NPPM4
GPM14
GPM24
XT4
4
0
BIT
Time, crystal oscillator enable and temperature conversion
in progress bit.
BUSY BIT (BUSY)
Busy Bit indicates temperature sensing is in progress. In this
mode, Alpha, Beta and ITRO registers are disabled and
cannot be accessed.
OSCILLATOR FAIL BIT (OSCF)
Oscillator Fail Bit indicates that the oscillator has stopped.
DAYLIGHT SAVING TIME CHANGE BIT (DSTADJ)
DSTADJ is the Daylight Saving Time Adjusted Bit. It
indicates the daylight saving time forward adjustment has
happened. If a DST Forward event happens, DSTADJ will be
set to “1”. The DSTADJ bit will stay high when DSTFD event
happens, and will be reset to “0” when the DST Reverse
event happens.
DSTADJ can be set to “1” for instances where the RTC
device is initialized during the DST Forward period. The
DSTE bit must be enabled when the RTC time is more than
one hour before the DST Forward or DST Reverse event
time setting, or the DST event correction will not happen.
DSTADJ is reset to “0” upon power-up. It will reset to “0”
when the DSTE bit in Register 15h is set to “0” (DST
disabled), but no time adjustment will happen.
ALARM BIT (ALM)
This bit announces if the alarm matches the real time clock. If
there is a match, the respective bit is set to “1”. This bit can be
manually reset to “0” by the user or automatically reset by
enabling the auto-reset bit (see ARST bit). A write to this bit in
the SR can only set it to “0”, not “1”. An alarm bit that is set by
an alarm occurring during an SR read operation will remain
set after the read operation is complete.
ADDR
ALP_H3
NPPM3
GPM13
GPM23
07h
XT3
3
0
BUSY OSCF DSTDJ ALM LVDD LBAT85 LBAT75 RTCF
7
NPPM10
ALP_H2
NPPM2
GPM12
GPM22
XT2
2
TABLE 2. STATUS REGISTER (SR)
6
ALP_H1
NPPM1
NPPM9
GPM11
GPM21
XT1
1
5
4
ALP_H0
NPPM0
NPPM8
GPM10
GPM20
XT0
0
3
RANGE
00 to FF
00 to 07
00 to FF
00 to 7F
00 to FF
00 to FF
2
December 18, 2008
DEFAULT
1
FN6668.4
XXh
XXh
00h
00h
00h
00h
0