isl12022m Intersil Corporation, isl12022m Datasheet - Page 15

• Manufacturer Part Number: isl12022m
• Description: Real Time Clock With Embedded Crystal, ??5ppm Accuracy
• Manufacturer: Intersil Corporation

Power Supply Control Register (PWR_VDD)
CLEAR TIME STAMP BIT (CLRTS)
This bit clears Time Stamp V
Stamp Battery to V
is 0 (CLRTS = 0) and the Enabled setting is 1 (CLRTS = 1).
V
These bits set the trip level for the V
V
LVDD bit in the Status Register is set to “1”. See Table 6.
Battery Voltage Trip Voltage Register (PWR_VBAT)
This register controls the trip points for the two V
with levels set to approximately 85% and 75% of the nominal
battery level.
RESEAL BIT (RESEALB)
This is the Reseal bit for actively disconnecting the V
from the internal circuitry. Setting this bit allows the device to
disconnect the battery and eliminate standby current drain
while the device is unused. Once V
reset and the V
circuitry.
The application for this bit involves placing the chip on a
board with a battery and testing the board. Once the board is
tested and ready to ship, it is desirable to disconnect the
battery to keep it fresh until the board or unit is placed into
final use. Setting RESEALB = “1” initiates the battery
disconnect, and after V
again, the RESEAL bit is cleared to “0”.
BATTERY LEVEL MONITOR TRIP BITS (VB85TP <2:0>)
Three bits select the first alarm (85% of Nominal V
the battery voltage monitor. There are total of 7 levels that could
09h
0Ah
ADDR 7
ADDR
DD
DD
V
DD
has dropped below a preset level. In this event, the
BROWNOUT TRIP VOLTAGE BITS (V
0
0
0
0
1
1
Trip2
D RESEALB VB85Tp2 VB85Tp1 VB85Tp0 VB75Tp2 VB75Tp1 VB75Tp0
CLRTS
7
6
BAT
TABLE 6. V
6
0
DD
V
pin is then connected to the internal
DD
5
5
0
Registers (TSB2V). The default setting
0
0
1
1
0
0
Trip1
DD
4
0
power is cycled down and up
DD
DD
15
TABLE 7.
4
3
0
TRIP LEVELS
to Battery (TSV2B) and Time
DD
V
V
DD
DD
DD
is powered up, this bit is
0
1
0
1
0
1
Trip0
3
2
Trip2 V
alarm, indicating that
DD
DD
2
TRIP<2:0>)
BAT
BAT
1
Trip1 V
VOLTAGE
BAT
2.295
2.550
2.805
3.060
4.250
4.675
TRIP
) level for
(V)
alarms,
1
pin
DD
ISL12022M
0
Trip0
0
be selected for the first alarm. Any of the of levels could be
selected as the first alarm with no reference as to nominal
Battery voltage level. See Table 8.
BATTERY LEVEL MONITOR TRIP BITS (VB75TP <2:0>)
Three bits select the second alarm (75% of Nominal V
level for the battery voltage monitor. There are total of 7 levels
that could be selected for the second alarm. Any of the of levels
could be selected as the second alarm with no reference as to
nominal Battery voltage level. See Table 9.
Initial AT and DT Setting Register (ITRO)
These bits are used to trim the initial error (at room
temperature) of the crystal. Both Digital Trimming (DT) and
Analog Trimming (AT) methods are available. The digital
trimming uses clock pulse skipping and insertion for
frequency adjustment. Analog trimming uses load
capacitance adjustment to pull the oscillator frequency. A
range of +62.5ppm to -61.5ppm is possible with combined
digital and analog trimming.
Initial values for the ITR0 register are preset internally and
recalled to RAM registers on power-up. These values are
pre-set in device production and are READ-ONLY. They
cannot be overwritten by the user. If an application
requires adjustment of the IATR bits outside the preset
values, the user should contact Intersil.
VB85Tp2
VB75Tp2
TABLE 9. BATTERY LEVEL MONITOR TRIP BITS
0
0
0
0
1
1
1
0
0
0
0
1
1
1
(VB75TP <2:0>)
TABLE 8. VB85T ALARM LEVEL
VB85Tp1
VB75Tp1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
VB85Tp0
VB75Tp0
0
1
0
1
0
1
0
0
1
0
1
0
1
0
BATTERY ALARM
BATTERY ALARM
TRIP LEVEL
TRIP LEVEL
December 18, 2008
2.125
2.295
2.550
2.805
3.060
4.250
4.675
1.875
2.025
2.250
2.475
2.700
3.750
4.125
(V)
(V)
BAT
FN6668.4
)