isl3874 Intersil Corporation, isl3874 Datasheet - Page 21

• Manufacturer Part Number: isl3874
• Description: Wireless Lan Integrated Medium Access Controller With Baseband Processor With Mini-pci
• Manufacturer: Intersil Corporation

For the 1 and 2Mbps modes, the transmitter accepts data
from the external source, scrambles it, differentially encodes
it as either DBPSK or DQPSK, and spreads it with the BPSK
PN sequence. The baseband digital signals are then output
to the external IF modulator.
For the CCK modes, the transmitter inputs the data and
partitions it into nibbles (4 bits) or bytes (8 bits). At 5.5Mbps, it
uses two of those bits to select one of 4 complex spread
sequences from a table of CCK sequences and then QPSK
modulates that symbol with the remaining 2 bits. Thus, there
are 4 possible spread sequences to send at four possible
carrier phases, but only one is sent. This sequence is then
modulated on the I and Q outputs. The initial phase reference
for the data portion of the packet is the phase of the last bit of
the header. At 11Mbps, one byte is used as above where 6 bits
are used to select one of 64 spread sequences for a symbol
and the other 2 are used to QPSK modulate that symbol. Thus,
the total possible number of combinations of sequence and
carrier phases is 256. Of these only one is sent.
MODULATION
DQPSK
DBPSK
DATA
CCK
CCK
SYMBOL
I vs. Q
Q
DATA
RATE
RATE
CHIP
I
OUT
OUT
1 BIT ENCODED TO
A/D SAMPLE CLOCK
802.11 DSSS BPSK
(TRUE-INVERSE)
ONE OF 2 CODE
BARKER
11 CHIPS
WORDS
11 MC/S
1 MS/S
1Mbps
(MHz)
21
22
22
22
22
TABLE 15. BIT RATE TABLE EXAMPLES FOR MCLK = 44MHz
2 BITS ENCODED
TO ONE OF
4 CODE WORDS
802.11 DSSS QPSK
FIGURE 12. MODULATION MODES
TX SETUP CR 5
BITS 1, 0
BARKER
11 MC/S
1 MS/S
2Mbps
11 CHIPS
00
01
10
11
ISL3874
The bit rate Table 15 shows examples of the bit rates and
the symbol rates and Figure 12 shows the modulation
schemes.
Header/Packet Description
The ISL3874 is designed to handle packetized Direct
Sequence Spread Spectrum (DSSS) data transmissions. The
ISL3874 generates its own preamble and header information. It
uses two packet preamble and header configurations. The first
is backwards compatible with the existing IEEE 802.11-1997 1
and 2Mbps modes and the second is the optional shortened
mode which maximizes throughput at the expense of
compatibility with legacy equipment.
In the long preamble mode, the device uses a
synchronization preamble of 128 symbols along with a
header that includes four fields. The preamble is all 1’s
(before entering the scrambler) plus a start frame delimiter
(SFD). The actual transmitted pattern of the preamble is
RX SIGNAL CR 63
SPREAD FUNCTIONS
4 BITS ENCODED
BITS 7, 6
COMPLEX CCK
CODE WORDS
TO ONE OF 16
5.5Mbps CCK
00
01
10
11
1.375 MS/S
COMPLEX
11 MC/S
8 CHIPS
DATA RATE
(Mbps)
5.5
11
1
2
SPREAD FUNCTIONS
8 BITS ENCODED
COMPLEX CCK
TO ONE OF 256
CODE WORDS
11Mbps CCK
1.375 MS/S
COMPLEX
11 MC/S
8 CHIPS
SYMBOL RATE
(MSPS)
1.375
1.375
1
1