isl3874 Intersil Corporation, isl3874 Datasheet - Page 4

• Manufacturer Part Number: isl3874
• Description: Wireless Lan Integrated Medium Access Controller With Baseband Processor With Mini-pci
• Manufacturer: Intersil Corporation

PIN NAME
HDEVSEL
HFRAME
HRESET
HSERR
HPERR
HIDSEL
HTRDY
HSTOP
HPCLK
HIRDY
HINTA
HREQ
HGNT
HPAR
HPME
HBE0
NUMBER
H16
B15
A15
A16
B16
C16
D15
D16
B13
C11
PIN
C6
D6
B7
C7
A7
B8
5V Tol, CMOS, BiDir PCI bus commands and byte enables. HBE0 applies to byte 0 (HAD7-HAD0).
CMOS, Output
5V Tol, CMOS, Input PCI reset.
5V Tol, BiDir
5V Tol, CMOS, BiDir PCI initiator ready. HIRDY indicates the PCI bus initiators ability to complete the current data phase
5V Tol, CMOS, BiDir PCI target ready. HTRDY indicates the primary bus targets ability to complete the current data
CMOS, Output
CMOS, Output
5V Tol, CMOS, BiDir PCI cycle stop signal. HSTOP is driven by a PCI target to request the initiator to stop the current
5V Tol, CMOS, BiDir PCI device select. The ISL3874 asserts HDEVSEL to claim a PCI cycle as the target device. As a
5V Tol, CMOS, BiDir PCI bus parity. In all PCI bus read and write cycles, the ISL3874 calculates even parity across the
5V Tol, CMOS, ST
Input
5V Tol, CMOS,
Input
5V Tol, CMOS, BiDir PCI bus parity.
5V Tol, CMOS,
Input
CMOS, Output
PIN I/O TYPE
4
TABLE 1. HOST INTERFACE PINS (Continued)
PCI Bus Interrupt A
PCI cycle frame. FRAME is driven by the initiator of a bus cycle. FRAME is asserted to indicate
that a bus transaction is beginning, and data transfers continue while this signal is asserted. When
FRAME is deasserted, the PCI bus transaction is in the final data phase.
of the transaction. A data phase is completed on a rising edge of PCLK where both HIRDY and
HTRDY are asserted. Until HIRDY and HTRDY are both sampled asserted, wait states are inserted.
phase of the transaction. A data phase is completed on a rising edge of PCLK when both HIRDY
and HTRDY are asserted. Until both HIRDY and HTRDY are asserted, wait states are inserted.
PCI bus request. HREQ is asserted by the ISL3874 to request access to the PCI bus as an initiator.
PCI system error. HSERR is an output that is pulsed from the ISL3874 when enabled through the
command register indicating a system error has occurred. The ISL3874 need not be the target of
the PCI cycle to assert this signal. When HSERR is enabled in the control register, this signal also
pulses, indicating that an address parity error has occurred on a CardBus interface.
PCI bus transaction. HSTOP is used for target disconnects and is commonly asserted by target
devices that do not support burst data transfers.
PCI initiator on the bus, the ISL3874 monitors HDEVSEL until a target responds. If no target
responds before timeout occurs, the ISL3874 terminates the cycle with an initiator abort.
HD31-HAD0 and BE3-BE0 buses. As an initiator during PCI cycles, the ISL3874 outputs this parity
indicator with a one-PCLK delay. As a target during PCI cycles, the calculated parity is compared
to the initiator parity indicator. A compare error results in the assertion of a parity error (PERR).
PCI bus grant. HGNT is driven by the PCI bus arbiter to grant the ISL3874 access to the PCI bus
after the current data transaction has completed. HGNT may or may not follow a PCI bus request,
depending on the PCI bus parking algorithm.
HPCLK provides timing for all transactions on the PCI bus. All PCI signals are sampled at the rising
edge of PCLK.
Initialization device select. HIDSEL selects the ISL3874 during configuration space accesses.
HIDSEL can be connected to one of the upper 24 PCI address lines on the PCI bus.
Power Management Event Output. HPME provides output for PME signals.
ISL3874
DESCRIPTION