isl3873 Intersil Corporation, isl3873 Datasheet - Page 4

• Manufacturer Part Number: isl3873
• Description: Wireless Lan Integrated Medium Access Controller With Baseband Processor
• Manufacturer: Intersil Corporation

PJ4
PJ5
PJ6
PJ7
PK0
PK1
PK2
PK3
PK4
PK7
PL3
PL7
CLKIN
XTALIN
XTALOUT
CLKOUT
BBP_CLK
RX_IF_AGC
RX_RF_AGC
RX_IF_DET
RXI,
RXQ,
TX_AGC_IN
TX_IF_AGC
TXI
TXQ
PJ0
PJ1
PJ2
TCLKIN (CS_)
PIN NAME
PIN NAME
PIN NAME
PIN NAME
PIN NAME
CMOS BiDir, 2mA
CMOS BiDir, 2mA, 50K Pull Up
CMOS BiDir, 2mA
CMOS BiDir, 2mA, 50K Pull Up
CMOS BiDir, 2mA, ST, 50K Pull Down
CMOS BiDir, 2mA, 50K Pull Down
CMOS BiDir, 2mA, 50K Pull Down
CMOS BiDir, 2mA
CMOS BiDir, 2mA
CMOS BiDir, 2mA
CMOS BiDir, 2mA
CMOS BiDir, 2mA, Pull Down
CMOS Input, 50K Pull Down
Analog Input
CMOS Output, 2mA
CMOS, TS Output, 2mA
Input
CMOS BiDir
CMOS BiDir, 50K Pull Down
CMOS BiDir, 50K Pull Down
CMOS BiDir
PIN I/O TYPE
PIN I/O TYPE
O
O
O
O
O
PIN I/O TYPE
I
I
I
I
4
MAC RADIO INTERFACE AND GENERAL PURPOSE PORT PINS
PIN I/O TYPE
PIN I/O TYPE
BASEBAND PROCESSOR TRANSMITTER PORT PINS
BASEBAND PROCESSOR RECEIVER PORT PINS
Input to the transmit power A/D converter for transmit AGC control
Analog drive to the transmit IF power control
TX Spread baseband I digital output data. Data is output at the chip rate. Balanced differential 23+/24-
TX Spread baseband Q digital output data. Data is output at the chip rate. Balanced differential
29+/30-
Analog drive to the IF AGC control
Drive to the RF AGC stage attenuator. CMOS digital
Analog input to the receive power A/D converter for AGC control
Analog input to the internal 6-bit A/D of the In-phase received data. Balanced differential 10+/11-
Analog input to the internal 6-bit A/D of the Quadrature received data. Balanced differential 13+/14-
SERIAL EEPROM PORT PINS
SCLK, Serial Clock
SD, Serial Data Out
MISO, Serial Data IN
CS_, Chip Select
CLOCKS PORT PINS
ISL3873
PE1
LE_IF
LED1
RADIO_PE
LE_RF
SYNTHCLK
SYNTHDATA
PA_PE
PE2
CAL_EN
TR_SW_BAR
TR_SW
External Clock Input to MCLK prescaler (at >= 2X Desired MCLK
Frequency, Typically 44-48MHz)
32.768kHz Crystal Input
32.768kHz Crystal Output
Internal Clock Output (Selectable as MCLK, TCLK, or TOUT0)
Baseband Processor Clock. The nominal frequency for this clock is
44MHz. This is used internally to generate divide by 2 and 4 for the
transceiver clock
DESCRIPTION
DESCRIPTION
DESCRIPTION OF FUNCTION
(IF OTHER THAN I/O PORT)
DESCRIPTION
DESCRIPTION