isl9444 Intersil Corporation, isl9444 Datasheet - Page 18

• Manufacturer Part Number: isl9444
• Manufacturer: Intersil Corporation

allowing fewer or less expensive capacitors, and reducing the
shielding requirements for EMI. The typical operating curves show
the synchronized 180° out-of-phase operation.
Power Failure Monitor
The ISL9444 has a Power-Failure Monitor that helps to monitor
an additional critical voltage on the Power-Fail Input (PFI) pin. For
example, the PFI pin could be used to provide an early power-fail
warning, detect a low-battery condition, or simply monitor a
power supply. An external resistor divider network is needed to
provide monitoring of voltages greater than 1.22V. The threshold
voltage is set according to Equation 6 (see Typical Application on
page 7).
PFO goes low whenever the PFI pin voltage is less than the 1.22V
threshold voltage.
Gate Control Logic
The gate control logic translates generated PWM signals into gate
drive signals providing amplification, level shifting and
shoot-through protection. The gate drivers have circuitry that helps
optimize the IC performance over a wide range of operational
conditions. As MOSFET switching times can vary dramatically from
type to type and with input voltage, the gate control logic provides
adaptive dead time by monitoring real gate waveforms of both the
upper and the lower MOSFETs. Shoot-through control logic provides
a 16ns dead-time to ensure that both the upper and lower MOSFETs
will not turn on simultaneously causing a shoot-through condition.
Gate Drivers
The low-side gate drivers are supplied from VCC_5V and provide a
peak sink current of 2A and source current of 800mA for each
PWM channel. The high-side gate drivers are also capable of
delivering the same currents as the low-side gate drivers.
Gate-drive voltage for the upper N-Channel MOSFETs are
generated by flying capacitor boot circuits. A boot capacitor
connected from the BOOT pin to the PHASE node provides power
to the high-side MOSFET driver. To limit the peak current in the IC,
an external resistor may be placed between the BOOT pin and the
boot capacitor. This small series resistor also damps any
oscillations caused by the resonant tank of the parasitic
inductances in the traces of the board and the FET’s input
capacitance.
At start-up, the low-side MOSFET turns on first and forces PHASE
to ground in order to charge the BOOT capacitor to 5V. After the
low-side MOSFET turns off, the high-side MOSFET is turned on by
closing an internal switch between BOOT and UGATE. This
provides the necessary gate-to-source voltage to turn on the
upper MOSFET, an action that boosts the 5V gate drive signal
above VIN. The current required to drive the upper MOSFET is
drawn from the internal 5V regulator.
For optimal EMI performance or reducing phase node ringing, a
small resistor might be placed between these pins to the positive
terminal of the bootstrap capacitors.
VPFITH
=
1.22V
×
R14
---------------------------- -
R15
+
R15
18
(EQ. 6)
ISL9444
Adaptive Dead Time
The ISL9444 incorporates an adaptive dead time algorithm on
the synchronous buck PWM controllers that optimizes operation
with varying MOSFET conditions. This algorithm provides
approximately 16ns of dead time between switching the upper
and lower MOSFET’s. This dead time is adaptive and allows
operation with different MOSFET’s without having to externally
adjust the dead time using a resistor or capacitor. During turn-off
of the lower MOSFET, the LGATE voltage is monitored until it
reaches a threshold of 1V, at which time the UGATE is released to
rise. Adaptive dead time circuitry monitors the upper MOSFET
gate voltage during UGATE turn-off. Once the upper MOSFET
gate-to-source voltage has dropped below a threshold of 1V, the
LGATE is allowed to rise. It is recommended to not use a resistor
between UGATE and LGATE and the respective MOSFET gates as
it may interfere with the dead time circuitry.
Internal Bootstrap Diode
The ISL9444 has integrated bootstrap diodes to help reduce total
cost and reduce layout complexity. Simply adding an external
capacitor across the BOOT and PHASE pins completes the
bootstrap circuit. The bootstrap capacitor must have a maximum
voltage rating above the maximum input voltage plus 5V. The
bootstrap capacitor can be chosen from Equation 7.
Where Q
charge the gate of the upper MOSFET. The ΔV
as the allowable droop in the rail of the upper drive.
As an example, suppose an upper MOSFET has a gate charge
(QGATE) of 25nC at 5V and also assume the droop in the drive
voltage over a PWM cycle is 200mV. One will find that a
bootstrap capacitance of at least 0.125µF is required. The next
larger standard value capacitance of 0.22µF should be used. A
good quality ceramic capacitor is recommended.
The internal bootstrap Schottky diodes have a resistance of 1.5Ω
(typ) at 800mA. Combined with the resistance RBOOT, this could
lead to the boot capacitor charging insufficiently in cases where
the bottom MOSFET is turned on for a very short time. If such
C
BOOT
≥
-------------------- -
ΔV
GATE
Q
GATE
BOOT
FIGURE 27. UPPER GATE DRIVER CIRCUIT
is the amount of gate charge required to fully
ISL9444
UGATE
PHASE
VCC_5V
BOOT
R
BOOT
SCHOTTKY
EXTERNAL
OPTIONAL
C
B
BOOT
VIN
term is defined
May 23, 2011
FN7665.0
(EQ. 7)