isl9444 Intersil Corporation, isl9444 Datasheet - Page 3

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isl9444

Manufacturer Part Number
isl9444
Description
Manufacturer
Intersil Corporation
Datasheet

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Pin Descriptions
PIN
10
11
12
13
14
15
16
17
18
19
20
21
22
23
6
7
8
9
MODE/SYNC
PG3_DLY
PGOOD1
PGOOD2
PGOOD3
EN/SS1
OCSET1
OCSET2
TK/SS2
OCSET3
TK/SS3
NAME
SGND
FB1
EN2
FB2
FB3
EN3
RT
This pin provides an enable/disable function and soft-starting for PWM1 output. The output is disabled when the pin is
pulled to GND. During start-up, a regulated 1.55µA soft-start current charges an external capacitor connected at this pin.
When the voltage on the EN/SS1 pin reaches 1.3V, the PWM1 output becomes active. From 1.3V to 2.0V, the reference
voltage of the PWM1 is clamped to the voltage at EN/SS1 minus 1.3V. The capacitance of the soft-start capacitors sets
the soft-starting time and enable delay time. Setting the soft-starting time too short might create undesirable overshoot
at the output during start-up. VCC_5V UVLO discharges the EN/SS1 via an internal MOSFET.
PWM1 feedback input. Connect FB1 to a resistive voltage divider from the output of PWM1 to GND to adjust the output
voltage.
A resistor from this pin to ground adjusts the overcurrent threshold for PWM1.
A resistor from this pin to ground adjusts the switching frequency from 200kHz to 1.2MHz. The switching frequency of
the PWM controller is determined by the resistor, R
R
where t
Open drain logic output used to indicate the status of the PWM1 output voltage. This pin is pulled down when the PWM1
output is not within ±11% of the nominal voltage.
Open drain logic output used to indicate the status of the PWM2 output voltage. This pin is pulled down when the PWM2
output is not within ±11% of the nominal voltage.
Open drain logic output used to indicate the status of the PWM3 output voltage. This pin is pulled down when the PWM3
output is not within ±11% of the nominal voltage.
A capacitor connected between this pin and ground sets a delay between PWM3 output voltage reaching ±11% of
regulation and PGOOD3 going high. There is no delay when PWM3 goes out of regulation and PGOOD3 is pulled low.
Enable/Disable input for PWM2. The output of PWM2 is enabled when this pin is pulled HIGH, and disabled when this pin
is pulled LOW. PGOOD2 is pulled LOW 1µs after EN2 is pulled LOW. Do not leave this pin floating.
This is the small-signal ground common to all 3 controllers. It is suggested to route this separately from the high current
ground (PGND). SGND and PGND can be tied together if there is one solid ground plane with no noisy currents around the
chip. All voltage levels are measured with respect to this pin.
A resistor from this pin to ground adjusts the overcurrent threshold for PWM2.
PWM2 feedback input. Connect FB2 to a resistive voltage divider from the output of PWM2 to GND to adjust the output
voltage.
Dual function pin. The reference voltage of PWM2 is clamped to the voltage at TK/SS2 during start-up. When this pin is
used for tracking, another channel is configured as the master and the output voltage of the master channel is applied
to this pin via a resistor divider.
When used for soft-starting control, a soft-start capacitor is connected from this pin to GND. A regulated 1.55µA soft-starting
current charges up the soft-start capacitor. Value of the soft-start capacitor sets the PWM2 output voltage ramp.
A resistor from this pin to ground adjusts the overcurrent threshold for PWM3.
PWM3 feedback input. Connect FB3 to a resistive voltage divider from the output of PWM3 to GND to adjust the output
voltage.
Dual function pin. The reference voltage of PWM3 is clamped to the voltage at TK/SS3 during start-up. When this pin is
used for tracking, another channel is configured as the master and the output voltage of the master channel is applied
to this pin via a resistor divider.
When used for soft-starting control, a soft-start capacitor is connected from this pin to GND. A regulated 1.55µA soft-starting
current charges up the soft-start capacitor. Value of the soft-start capacitor sets the PWM3 output voltage ramp.
Enable/Disable input for PWM3. The output of PWM3 is enabled when this pin is pulled HIGH, and disabled when this pin
is pulled LOW. PGOOD3 is pulled LOW 1µs after EN3 is pulled LOW. Do not leave this pin floating.
Dual function pin. Tie this pin to ground or VCC_5V for light load operation mode selection. Connect this pin to ground to
select Diode Emulation Mode with pulse skipping at light load. While connected to VCC_5V, the controllers operate in
PWM Mode at light load.
Connect this pin to CLKOUT of another ISL9444 or an external clock for synchronization. The controller operates in PWM
at light load when synchronized with another ISL9444 or with an external clock.
T
=
3
(Continued)
(
23.36
SW
is the switching period in µs.
×
(
1.5 t
×
SW
0.36
)
) kΩ
ISL9444
T
,
FUNCTION
(EQ. 1)
May 23, 2011
FN7665.0

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