isl62883c Intersil Corporation, isl62883c Datasheet - Page 13

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isl62883c

Manufacturer Part Number
isl62883c
Description
Multiphase Pwm Regulator For Imvp-6.5? Mobile Cpus And Gpus
Manufacturer
Intersil Corporation
Datasheet

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Theory of Operation
Multiphase R
FIGURE 6. R
Master
Clock3
Clock1
Clock2
Crs1
Crs2
Crs3
COMP
PW M1
PW M2
PW M3
Clock
Vcrm
gmVo
VW
MASTER
CLOCK
Vcrs1
Vcrs2
Vcrs3
FIGURE 5. R
VW
VW
VW
VW
PRINCIPLES IN STEADY STATE
Vcrm
Vcrs2
3
COMP
Crm
3™
MODULATOR OPERATION
Clock3
MASTER CLOCK CIRCUIT
Clock2
Clock1
VW
Modulator
Vcrs3
3
gm
gm
gm
SLAVE CIRCUIT 1
SLAVE CIRCUIT 2
SLAVE CIRCUIT 3
MASTER
CLOCK
MODULATOR CIRCUIT
S
R
S
R
S
R
13
Q
Q
Q
Vcrs1
PWM1
PWM2
PWM3
Sequencer
Phase
Phase1
Phase2
Phase3
Hysteretic
W indow
Clock1
Clock2
Clock3
L1
L2
L3
I
I
I
L1
L2
L3
Vo
ISL62883C
Co
The ISL62883C is a multiphase regulators implementing
Intel™ IMVP-6.5™ protocol. It can be programmed for
1-, 2- or 3-phase operation. It uses Intersil patented
R
modulator combines the best features of fixed
frequency PWM and hysteretic PWM while eliminating
many of their shortcomings. Figure 5 conceptually
shows the ISL62883C multiphase R
circuit, and Figure 6 shows the operation principles.
A current source flows from the VW pin to the COMP
pin, creating a voltage window set by the resistor
between the two pins. This voltage window is called
VW window in the following discussion.
Inside the IC, the modulator uses the master clock
circuit to generate the clocks for the slave circuits. The
modulator discharges the ripple capacitor C
current source equal to g
factor. C
traversing between the VW and COMP voltages. It
resets to VW when it hits COMP, and generates a
one-shot master clock signal. A phase sequencer
distributes the master clock signal to the slave circuits.
If the ISL62883C is in 3-phase mode, the master clock
signal will be distributed to the three phases, and the
Clock1~3 signals will be 120° out-of-phase. If the
ISL62883C is in 2-phase mode, the master clock signal
will be distributed to Phases 1 and 2, and the Clock1
and Clock2 signals will be 180° out-of-phase. If the
FIGURE 7. R
3
Master
Clock3
Clock1
Clock2
PWM1
PWM2
PWM3
™ (Robust Ripple Regulator™) modulator. The R
Clock
Vcrm
rm
voltage V
PRINCIPLES IN LOAD INSERTION
RESPONSE
3
Vcrs2
Vcrs3
Vcrs1
MODULATOROPERATION
COMP
VW
crm
VW
is a sawtooth waveform
m
V
o
, where g
3
™ modulator
m
is a gain
rm
March 18, 2010
with a
FN7557.1
3

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