SB16C1058-TQFP128 IK Semicon Co., Ltd, SB16C1058-TQFP128 Datasheet - Page 27
SB16C1058-TQFP128
Manufacturer Part Number
SB16C1058-TQFP128
Description
Octal-uart Controller With 256-byte Fifo
Manufacturer
IK Semicon Co., Ltd
Datasheet
1.SB16C1058-TQFP128.pdf
(66 pages)
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Figure 7:
XTAL1
XTAL2
Prescaler and Baud Rate Generator Block Diagram
OSCILLATOR
INTERNAL
6.9 Programmable Baud Rate Generator
LOGIC
■
■
■
The IN16C1058 has a programmable baud rate generator with a prescaler. The prescaler
is controlled by MCR[7], as shown in Figure 7. The MCR[7] sets the prescaler to divide
the clock frequency by 1 or 4. And the baud rate generator further divides this clock
frequency by a programmable divisor (DLL and DLM) between 1 and (2
16X sampling rate clock of the serial data rate. The sampling rate clock is used by
transmitter for data bit shifting and receiver for data sampling.
The divisor of the baud rate generator is:
MCR[7] is cleared to ‘0’ (prescaler = 1), when CLKSEL input is in high state after reset.
MCR[7] is set to ‘1’ (prescaler = 4), when CLKSEL input is in low state after reset.
DLL and DLM must be written to in order to program the baud rate. DLL and DLM are the
least and most significant byte of the baud rate divisor, respectively. If DLL and DLM are
both zero, the IN16C1058 is effectively disabled, as no baud clock will be generated.
Table 6 shows the baud rate and divisor value for prescaler with divide by 1 as well as
crystal with frequency 1.8432MHz, 3.6864MHz, 7.3728MHz, and 14.7456MHz,
respectively.
Figure 8 shows the crystal clock circuit reference.
RXD input receives the data start bit transition.
Data byte is loaded to the TX FIFO or THR.
NCTS, NDSR, NDCD, and NRI inputs are changed.
Divisor =
(DIVIDE BY 1)
(DIVIDE BY 4)
PRESCALER
PRESCALER
(
LOGIC
LOGIC
XTAL1 Crystal Input Frequency
OCTAL UART WITH 256-BYTE FIFO
(Desired Baud Rate x 16)
MCR[7] = 0
MCR[7] = 1
Prescaler
REFERENCE
CLOCK
PROGAMMABLE
GENERATOR
BAUD RATE
DIVISOR
LOGIC
)
IN16C1058
JUNE 2009
16
INTERNAL
BAUD RATE
CLOCK FOR
TRANSMITTER
AND
RECEIVER
– 1) to obtain a
REV 1.0
27
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