S25FL008A Meet Spansion Inc., S25FL008A Datasheet - Page 19

• Manufacturer Part Number: S25FL008A
• Description: 8-megabit Cmos 3.0 Volt Flash Memory With 50 Mhz Spi Bus Interface
• Manufacturer: Meet Spansion Inc.

9.8
June 29, 2007 S25FL008A_00_B2
Page Program (PP)
Note
As defined by the values in the Block Protect (BP2, BP1, BP0) bits of the Status Register, as shown in
Table 9.3
either by setting the SRWD bit after driving W# low, or by driving W# low after setting the SRWD bit.
However, the device disables HPM only when W# is driven high.
Note that HPM only protects against changes to the status register. Since BP2:BP0 cannot be changed in
HPM, the size of the protected area of the memory array cannot be changed. Note that HPM provides no
protection to the memory array area outside that specified by BP2:BP0 (Software Protected Mode, or SPM).
If W# is permanently tied high, HPM can never be activated, and only the SPM (BP2:BP0 bits of the Status
Register) can be used.
The Page Program (PP) command changes specified bytes in the memory array (from 1 to 0 only). A WREN
command is required prior to writing the PP command.
The host system must drive CS# low, and then write the PP command, three address bytes, and at least one
data byte on SI. CS# must be driven low for the entire duration of the PP sequence. The command sequence
is shown in
The device programs only the last 256 data bytes sent to the device. If the number of data bytes exceeds this
limit, the bytes sent before the last 256 bytes are discarded, and the device begins programming the last 256
bytes sent at the starting address of the specified page. This may result in data being programmed into
different addresses within the same page than expected. If fewer than 256 data bytes are sent to device, they
are correctly programmed at the requested addresses.
The host system must drive CS# high after the device has latched the 8th bit of the data byte, otherwise the
device does not execute the PP command. The PP operation begins as soon as CS# is driven high. The
device internally controls the timing of the operation, which requires a period of t
be read to check the value of the Write In Progress (WIP) bit while the PP operation is in progress. The WIP
bit is 1 during the PP operation, and is 0 when the operation is completed. The device internally resets the
Write Enable Latch to 0 before the operation completes (the exact timing is not specified).
The device does not execute a Page Program (PP) command that specifies a page that is protected by the
Block Protect bits (BP2:BP0) (see
W# Signal
1
1
0
0
shows that neither W# or SRWD bit by themselves can enable HPM. The device can enter HPM
SRWD Bit
Figure 9.8 on page 20
1
0
0
1
Software
Protected (SPM)
Hardware
Protected (HPM)
Figure 9.7 Write Status Register (WRSR) Command Sequence
CS#
SCK
D a t a
SI
SO
Mode
Mode 3
Mode 0
Hi-Z
Table 7.1 on page
S h e e t
and
Status Register is writable (if the WREN
command has set the WEL bit). The
values in the SRWD, BP2, BP1 and
BP0 bits can be changed.
Status Register is Hardware write
protected. The values in the SRWD,
BP2, BP1 and BP0 bits cannot be
changed.
0
Write Protection of the Status
Table 9.4 on page
S25FL008A
1
Table 9.3 Protection Modes
2
Command
3
4
Register
5
6
12).
7
MSB
7
8 9 10 11 12 13 14 15
23.
6
Status Register In
5
4
3
2
program and erase
program and erase
Protected against
Protected against
Protected Area
1
(See Note)
commands
commands
0
Table 7.1 on page
PP
. The Status Register may
Ready to accept Page
Ready to accept Page
Program and Sector
Program and Sector
Unprotected Area
Erase commands
Erase commands
(See Note)
12.
19