mcf51ag96 Freescale Semiconductor, Inc, mcf51ag96 Datasheet - Page 2

• Manufacturer Part Number: mcf51ag96
• Description: Coldfire Microcontroller Covers Mcf51ag128 And Mcf51ag96 Mcf51ag128 Coldfire Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

• System Clock Sources
• Peripherals
• Input/Output
2
– Oscillator (XOSC) — Loop-control pierce oscillator; crystal or ceramic resonator range of 31.25 kHz to 38.4 kHz or 1
– Internal Clock Source (ICS) — Frequency-locked-loop (FLL) controlled by internal or external reference; trimmable
– ADC — 24 analog inputs with 12 bits resolution; output formatted in 12-, 10- or 8-bit right-justified format; single or
– PDB — 16-bit of resolution with prescaler; seven possible trigger events input; positive transition of trigger event signal
– iEvent — User programmable combinational boolean output using the four selected iEvent input channels for use as
– FTM — Two 6-channel flexible timer/PWM modules with DMA request option; deadtime insertion is available for each
– TPM — 16-bit free-running or modulo up/down count operation; two channels, each channel may be input capture, output
– CRC — High speed hardware CRC generator circuit using 16-bit shift register; CRC16-CCITT compliancy with x
– HSCMP — Two analog comparators with selectable interrupt on rising edge, falling edge, or either edges of comparator
– IIC — Compatible with IIC bus standard and SMBus version 2 features; up to 100 kbps with maximum bus loading;
– SCI — Two serial communications interface modules with optional 13-bit break; full-duplex, standard non-return-to-zero
– SPI — Two serial peripheral interfaces with full-duplex or single-wire bidirectional option; double-buffered transmitter
– Up to 69 GPIOs and one Input-only pin
– Interrupt or DMA request with selectable polarity on all input pins
– Programmable glitch filter, hysteresis and configurable pull up/down device on all input pins
– Configurable slew rate and drive strength on all output pins
– Independent pin value register to read logic level on digital pin
– Up to 16 rapid general purpose I/O (RGPIO) pins connected to the processor’s local 32-bit platform bus with set, clear,
MHz to 16 MHz
internal reference allows 0.2% resolution and 2% deviation (1% across 0 to 70 ºC)
continuous conversion (automatic return to idle after single conversion); interrupt or DMA request when conversion
complete; operation in low-power modes for lower noise operation; asynchronous clock source for lower noise operation;
selectable asynchronous hardware conversion triggers from RTC, PDB, or iEvent; dual samples based on hardware
triggers during ping-pong mode; on-chip temperature sensor
initiates the counter; support continuous trigger or single shot, bypass mode; supports two triggered delay outputs or ORed
together; pulsed output could be used for HSCMP windowing signal
interrupt requests, DMA transfer requests, or hardware triggers
complementary channel pair; channels operate as pairs with equal outputs, pairs with complimentary outputs or
independent channels (with independent outputs); 16-bit free-running counter; the load of the FTM registers which have
write buffer can be synchronized; write protection for critical registers; backwards compatible with TPM
compare, or edge-aligned PWM; one interrupt per channel plus terminal count interrupt
+ x
output; the positive and negative inputs of the comparator are both driven from 4-to-1 muxes; programmable voltage
reference from two internal DACs; support DMA transfer
multi-master operation; software programmable for one of 64 different serial clock frequencies; programmable slave
address and glitch input filter; interrupt driven byte-by-byte data transfer; arbitration lost interrupt with automatic mode
switching from master to slave; calling address identification interrupt; bus busy detection; broadcast and 10-bit address
extension; address matching causes wake-up when MCU is in Stop3 mode; DMA support
(NRZ) format; double-buffered transmitter and receiver with separate enables; 13-bit baud rate selection with /32
fractional divide; interrupt-driven or polled operation; hardware parity generation and checking; programmable 8-bit or
9-bit character length; receiver wakeup by idle-line or address-mark; address match feature in receiver to reduce
address-mark wakeup ISR overhead; 1/16 bit-time noise detection; DMA transmission for both transmit and receive
and receiver; master or slave mode operation; selectable MSB-first or LSB-first shifting; 8-bit or 16-bit data modes;
programmable transmit bit rate; receive data buffer hardware match feature; DMA transmission for transmit and receive
and faster toggle functionality
5
+ 1 polynomial; error detection for all single, double, odd, and most multi-bit errors; programmable initial seed value
MCF51AG128 ColdFire Microcontroller, Rev. 5
Freescale Semiconductor
16
+ x
12