c15bc1 aptina, c15bc1 Datasheet - Page 35

• Manufacturer Part Number: c15bc1
• Description: Mt9d014 1/4-inch 2mp Cmos Digital Image Sensor
• Manufacturer: aptina

Programming the PLL Divisors
Influence of ccp_data_format
PDF: 0526161444/Source:6112702771
MT0D014_DS - Rev. J 5/10 EN
The PLL divisors should be programmed while the MT9D014 is in the soft standby state.
After programming the divisors, it is necessary to wait for the VCO lock time before
enabling the PLL. The PLL is enabled by entering the streaming state.
An external timer needs to delay the entering of streaming mode by 1ms so that the PLL
can lock.
The effect of programming the PLL divisors while the MT9D014 is in the streaming state
is undefined.
R0x0112-3 (ccp_data_format) controls whether the pixel data interface will generate 10
bits per pixel or 8 bits per pixel. The raw output of the sensor core is 10 bits per pixel; the
two 8-bit modes represent a compressed data mode and a mode in which the two least
significant bits of the 10-bit data are discarded.
When the pixel data interface is generating 8 bits per pixel, op_pix_clk_div must be
programmed with the value 8. When the pixel data interface is generating 10 bits per-
pixel, op_pix_clk_div must be programmed with the value 10.
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MT9D014: 1/4-Inch 2Mp CMOS Digital Image Sensor
Aptina reserves the right to change products or specifications without notice.
©2007 Aptina Imaging Corporation. All rights reserved.
Preliminary
Clocking