ds42585 Advanced Micro Devices, ds42585 Datasheet
ds42585
Related parts for ds42585
ds42585 Summary of contents
Page 1
... PRELIMINARY DS42585 Stacked Multi-Chip Package (MCP) Flash Memory and SRAM Am29DL324D Bottom Boot 32 Megabit ( 8-Bit 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 8 Mbit ( 8-Bit/512 K x 16-Bit) Static RAM DISTINCTIVE CHARACTERISTICS MCP Features Power supply voltage of 2.7 to 3.3 volt High performance — ...
Page 2
... The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly re- duced in both modes. DS42585 ...
Page 3
... Unlock Bypass Command Sequence . . . . . . . . 24 Figure 3. Program Operation . . . . . . . . . . . . . . . 25 Chip Erase Command Sequence . . . . . . . . . . . . 25 Sector Erase Command Sequence . . . . . . . . . . . 25 Erase Suspend/Erase Resume Commands . . . . 26 Figure 4. Erase Operation . . . . . . . . . . . . . . . . . 26 Table 12. DS42585 Command Definitions . . . . 27 Write Operation Status . . . . . . . . . . . . . . . . . . . . . 28 DQ7: Data# Polling . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 5. Data# Polling Algorithm . . . . . . . . . . . 28 RY/BY#: Ready/Busy DQ6: Toggle Bit Figure 6 ...
Page 4
... Flash Erase And Programming Performance . . . 55 Flash Latchup Characteristics Package Pin Capacitance . . . . . . . . . . . . . . . . . . 55 Flash Data Retention . . . . . . . . . . . . . . . . . . . . . . 55 SRAM Data Retention . . . . . . . . . . . . . . . . . . . . . . 56 Figure 33. CE1#s Controlled Data Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Figure 34. CE2s Controlled Data Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 57 FLB073—73-Ball Fine-Pitch Grid Array Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 58 Revision A (May 22, 2001 DS42585 ...
Page 5
... A0 to A18 SA LB#s UB#s WE# OE# CE1#s CE2s CIOs Flash Memory RY/BY Bit Flash Memory DQ0 to DQ15/A– CCQ SS SSQ 8 M Bit DQ0 to DQ15/A–1 Static RAM DS42585 DS42585 SRAM DQ0 to DQ15/A–1 5 ...
Page 6
... FLASH MEMORY BLOCK DIAGRAM A0–A20 RY/BY# A0–A20 RESET# STATE CONTROL WE# & CE# COMMAND BYTE# REGISTER WP#/ACC DQ0–DQ15 A0–A20 Upper Bank Address Upper Bank X-Decoder Status Control X-Decoder Lower Bank Lower Bank Address DS42585 OE# BYTE# DQ0–DQ15 OE# BYTE# ...
Page 7
... Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compro- mised if the package body is exposed to temperatures above 150 C for prolonged periods of time. DS42585 Flash only A10 NC SRAM only B10 NC Shared D9 A15 ...
Page 8
... The state machine outputs dictate the function of the device. Tables 1 through 3 lists the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections de- scribe each of these operations in further detail. DS42585 DQ0–DQ15 RY/BY# ...
Page 9
... 8.5–12 9.0 ± 0 Don’t Care Sector Address and CE2s = V at the same time. IH the boot sectors protection will be removed. IH DS42585 ; SRAM Word Mode, CIOs = WP#/ACC DQ0– DQ7 DQ8–DQ15 (Note OUT OUT ...
Page 10
... 8.5–12 9.0 ± 0 Don’t Care Sector Address and CE2s = V at the same time. IH the boot sectors protection will be removed. IH DS42585 ; SRAM Byte Mode, CIOs = WP#/ACC RESET# DQ0–DQ7 DQ8–DQ15 (Note OUT H ...
Page 11
... 8.5–12 9.0 ± 0 Don’t Care Sector Address and CE2s = V at the same time. IH the boot sectors protection will be removed. IH DS42585 ; SRAM Byte Mode, CIOs = WP#/ACC RESET# DQ0–DQ7 DQ8–DQ15 (Note 4) H L/H D High-Z OUT H ...
Page 12
... Figure 21 shows how read and write cycles may be initiated for simultaneous operation with zero latency. I CC6 represent the current specifications for read-while-pro- gram and read-while-erase, respectively. DS42585 on this pin, the device auto- HH for operations other than accelerated pro- and I in the DC Characteristics table ...
Page 13
... The output pins are placed in the high impedance state. Table 4. Device Bank Division Bank 1 Sector Sizes Megabits Eight 8 Kbyte/4 Kword, thirty-one 64 Kbyte/32 Kword DS42585 ± 0.3 V, the de RESET# is CC4 ± 0.3 V, the standby cur- SS (during Embedded Algorithms). The (not during Embed- ...
Page 14
... DS42585 (x16) Address Range 000000h–000FFFh 001000h–001FFFh 002000h–002FFFh 003000h–003FFFh 004000h–004FFFh 005000h–005FFFh 006000h–006FFFh 007000h–007FFFh 008000h–00FFFFh 010000h–017FFFh 018000h–01FFFFh 020000h–027FFFh 028000h– ...
Page 15
... A20:A0 in word mode (CIOf=V IL SecSi Sector Addresses for Bottom Boot Devices Sector Address A20–A12 000000XXX DS42585 (x8) (x16) Address Range 100000h–107FFFh 108000h–10FFFFh 110000h–117FFFh 118000h–11FFFFh 120000h–127FFFh 128000h–12FFFFh 130000h–137FFFh 138000h–13FFFFh 140000h– ...
Page 16
... Kbytes That is, sector protection or unprotection for these two 8 Kbytes sectors depends on whether they were last protected or unprotected using the method described in “Sec- 8 Kbytes tor/Sector Block Protection and Unprotection”. 8 Kbytes DS42585 Sector/Sector Block A20–A12 Size 000000011 8 Kbytes 000000010 8 Kbytes 000000001 ...
Page 17
... Notes: 1. All protected sectors unprotected (If WP#/ACC = V outermost boot sectors will remain protected). 2. All previously protected sectors are protected once again. Figure 1. Temporary Sector Unprotect Operation DS42585 START RESET (Note 1) Perform Erase or Program Operations RESET ...
Page 18
... Reset PLSCNT = 1 Increment PLSCNT No Yes PLSCNT = 1000? Yes Device failed Sector Unprotect Algorithm DS42585 START PLSCNT = 1 RESET Wait First Write Temporary Sector Cycle = 60h? Unprotect Mode Yes No All sectors protected? Yes ...
Page 19
... Noise pulses of less than 5 ns (typical) on OE#, CE#f or WE# do not initiate a write cycle. Logical Inhibit Write cycles are inhibited by holding any one CE#f and WE# must be a logical zero while OE logical one. DS42585 This IH ID power- the device does not ac- LKO CC is greater than V ...
Page 20
... Query Unique ASCII string “QRY” 0059h 0002h Primary OEM Command Set 0000h 0040h Address for Primary Extended Table 0000h 0000h Alternate OEM Command Set (00h = none exists) 0000h 0000h Address for Alternate OEM Extended Table (00h = none exists) 0000h DS42585 Description ...
Page 21
... Erase Block Region 2 Information 0000h 0001h 0000h 0000h Erase Block Region 3 Information 0000h 0000h 0000h 0000h Erase Block Region 4 Information 0000h 0000h DS42585 Description pin present) PP pin present µs N µ s (00h = not supported (00h = not supported) ...
Page 22
... Not Supported Word Page Word Page ACC (Acceleration) Supply Minimum 0085h 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV ACC (Acceleration) Supply Maximum 0095h 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV Top/Bottom Boot Sector Flag 000Xh 02h = Bottom Boot Device, 03h = Top Boot Device DS42585 Description ...
Page 23
... A7–A0 in word mode (or the address 04h on A6–A-1 in byte mode) returns 01h if the sector is protected, or 00h unprotected. (Refer to Ta- bles 5–6 for valid sector addresses). The system must write the reset command to return to reading array data (or erase-suspend-read mode if the bank was previously in Erase Suspend). DS42585 23 ...
Page 24
... Figure 3 illustrates the algorithm for the program oper- ati on . Ref Operations table in the AC Characteristics section for parameters, and Figure 18 for timing diagrams. DS42585 any operation HH ...
Page 25
... WE# pulse in the command sequence. When the Embedded Erase algorithm is complete, the bank returns to reading array data and addresses are no longer latched. Note that while the Embedded Erase operation is in progress, the system can read data from the non-erasing bank. The system can de- DS42585 25 ...
Page 26
... Command Sequence (Notes 1, 2) Data Poll to Erasing Bank from System No Data = FFh? Erasure Completed Notes: 1. See Table 12 for erase command sequence. 2. See the section on DQ3 for information on the sector erase timer. Figure 4. Erase Operation DS42585 START Embedded Erase algorithm in progress Yes ...
Page 27
... Table 12. DS42585 Command Definitions Command Sequence (Note 1) Addr Read (Note 6) 1 Reset (Note 7) 1 XXX Word 555 Manufacturer ID 4 Byte AAA Word 555 Device ID 4 Byte AAA Word 555 SecSi Sector Factory 4 Protect (Note 9) Byte AAA Word 555 Sector Protect Verify ...
Page 28
... During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5. Figure 5. Data# Polling Algorithm DS42585 Yes No Yes Yes No ...
Page 29
... Reset Command Note: The system should recheck the toggle bit even if DQ5 = “1” because the toggle bit may stop toggling as DQ5 changes to “1.” See the subsections on DQ6 and DQ2 for more information. Figure 6. Toggle Bit Algorithm DS42585 No Yes Yes No Yes ...
Page 30
... DQ3 prior to and following each subsequent sector erase com- mand. If DQ3 is high on the second status check, the last command might not have been accepted. Table 13 shows the status of DQ3 relative to the other status bits. DS42585 ...
Page 31
... The device outputs array data if the system addresses a non-busy bank Table 13. Write Operation Status DQ7 DQ5 DQ6 (Note 2) (Note 1) DQ7# Toggle 0 Toggle 1 No toggle Data Data Data DQ7# Toggle DS42585 DQ2 DQ3 RY/BY# (Note 2) 0 N/A No toggle Toggle 0 0 N/A Toggle 1 Data Data ...
Page 32
... V f/V s for standard voltage range . . 2 3 Operating ranges define those limits between which the func- tionality of the device is guaranteed –2 +2 +0.5 V 2.0 V Figure 8. Maximum Positive DS42585 ) . . . . . . . . .–25°C to +85° Overshoot Waveform ...
Page 33
... CE1 MHz IL CE2s = MHz CE1#s = 0.2 V, CE2s = V s – 0.2V 1 MHz CC 1) CE1 CE2s = CE2s = V IL CE1 – 0.2V, CE2s – 0.2V CC CE2s 0.2V DS42585 Min Typ Max Unit 1.0 µA 35 µA 1.0 µA 35 µ 0.2 5 µA ...
Page 34
... OH CE1 CE2 = V , Other IH IL inputs = CE1#s V – 0.2 V, CE2 V – 0.2 V (CE1#s controlled) or CE2 0.2 V (CE2s controlled), CIOs = Other input = DS42585 Min Typ Max Unit 8.5 9.5 V 8.5 12.5 V 0. –0.4 CC 2.3 2 ns. Typical sleep mode current is ...
Page 35
... Figure 9. I Current vs. Time (Showing Active and Automatic Sleep Currents) CC1 Note 1500 2000 2500 Time Frequency in MHz Figure 10. Typical I vs. Frequency CC1 DS42585 3000 3500 4000 3 ...
Page 36
... Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels INPUTS Steady Changing from Changing from Does Not Apply Center Line is High Impedance State (High Z) Measurement Level DS42585 85 ns Unit 1 TTL gate 0.0–3 ...
Page 37
... AC CHARACTERISTICS SRAM CE#s Timing Parameter JEDEC Std Description — t CE#s Recover Time CCR E#f E1#s E2s Figure 13. Timing Diagram for Alternating Between SRAM to Flash CCR t CCR DS42585 Speed Test Setup Unit 85 — Min CCR t CCR 37 ...
Page 38
... Test Setup CE# Read Toggle and Data# Polling t RC Addresses Stable t ACC OEH t CE HIGH Z Figure 14. Read Operation Timings DS42585 85 ns Speed Min Max HIGH Z Output Valid Unit ns ns ...
Page 39
... Description Max Max Min Min Min Min Ready Reset Timings NOT during Embedded Algorithms Reset Timings during Embedded Algorithms t Ready t RP Figure 15. Reset Timings DS42585 85 ns Unit 20 µs 500 ns 500 µ ...
Page 40
... ELFH Data Output (DQ0–DQ7) Address DQ15 Input Output t FHQV The falling edge of the last WE# signal t SET ( HOLD AH and t specifications DS42585 85 ns Speed Typ Max Unit Data Output (DQ0–DQ7) Address Input Data Output (DQ0–DQ14) ...
Page 41
... Notes: 1. Not 100% tested. 2. See the “Flash Erase And Programming Performance” section for more information CE#f Low During Toggle Bit Read Toggle and Data# Polling Byte Word DS42585 85 ns Speed Unit Min Typ Max ...
Page 42
... WPH A0h t BUSY is the true data at the program address. OUT Figure 18. Program Operation Timings DS42585 Read Status Data (last two cycles WHWH1 Status D OUT VHH ...
Page 43
... These waveforms are for the word mode. Figure 20. Chip/Sector Erase Operation Timings 555h for chip erase WPH t DH 30h 10 for Chip Erase t BUSY DS42585 Read Status Data WHWH2 In Complete Progress ...
Page 44
... OEH GHWL Valid Out t SR/W Read Cycle Complement Complement Status Data Status Data DS42585 Valid PA Valid PA t CPH t CP Valid Valid In In CE#f Controlled Write Cycles VA High Z Valid Data True High Z True Valid Data ...
Page 45
... AHT AS t AHT t ASO t CEPH t OEPH t OE Valid Valid Status Status (first read) (second read) Enter Erase Suspend Program Erase Erase Suspend Suspend Read Program Figure 24. DQ2 vs. DQ6 DS42585 Valid Valid Data Status (stops toggling) Erase Resume Erase Erase Complete Read 45 ...
Page 46
... VIDR CE#f WE# RY/BY# Figure 25. Temporary Sector/Sector Block Unprotect Timing Diagram Min Min Min Min Program or Erase Command Sequence t RSP DS42585 85 ns Speed Unit 500 ns 250 VIDR ...
Page 47
... For sector protect For sector unprotect Figure 26. Sector/Sector Block Protect and Unprotect Timing Diagram Valid* Valid* Verify 60h 40h Sector/Sector Block Protect: 150 µs, Sector/Sector Block Unprotect DS42585 Valid* Status 47 ...
Page 48
... Not 100% tested. 2. See the “Flash Erase And Programming Performance” section for more information Min Byte Word DS42585 85 ns Speed Typ Max Unit µs ...
Page 49
... SA for sector erase 555 for chip erase Data# Polling GHEL t t WHWH1 CPH t BUSY for program PD for program 55 for erase 30 for sector erase 10 for chip erase is the data written to the device. OUT DS42585 PA DQ7# D OUT 49 ...
Page 50
... Output Data Hold from Address Change OH ddress ata Out Previous Data Valid Note: CE1 CE2s = WE Figure 28. SRAM Read Cycle—Address Controlled UB#s and/or LB DS42585 Min Max Unit ...
Page 51
... At any given temperature and voltage condition, t interconnection CO1 t CO2 OLZ t BLZ t LZ Data Valid Figure 29. SRAM Read Cycle (Max.) is less than t (Min.) both for a given device and from device to device HZ LZ DS42585 BHZ t OHZ 51 ...
Page 52
... (See Note (See Note 4) High applied in case a write ends as CE1#s or WE# going high low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when DS42585 Min Max Unit ...
Page 53
... (See Note 5) High-Z applied in case a write ends as CE1#s or WE# going high low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when DS42585 t (See Note Data Valid High-Z is measured from the beginning of write ...
Page 54
... Note 4) WP (See Note High-Z applied in case a write ends as CE1#s or WE# going high low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when DS42585 t (See Note Data Valid High-Z is measured from the beginning of write ...
Page 55
... V, one pin at a time. CC Test Setup OUT Test Conditions DS42585 Unit Comments sec Excludes 00h programming prior to erasure (Note 4) sec µs µs Excludes system level µs overhead (Note 5) sec , 1,000,000 cycles. Additionally, CC Min Max – ...
Page 56
... V = 3.0 V, CE1 (See Note) See data retention waveforms – 0.2 V (CE1#s controlled) or CE2s 0.2 V (CE2s controlled), CIOs = V Data Retention Mode t SDR CE1 0 Data Retention Mode t SDR CE2s £ 0.2 V DS42585 Min Typ Max Unit 1.5 3.3 – 0 RDR t RDR V µ ...
Page 57
... PHYSICAL DIMENSIONS FLB073—73-Ball Fine-Pitch Grid Array DS42585 57 ...
Page 58
... AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies DS42585 ...