ltc2195 Linear Technology Corporation, ltc2195 Datasheet - Page 20

• Manufacturer Part Number: ltc2195
• Description: Ltc2195/ltc2194/ltc2193 - 16-bit, 125/105/80msps Low Power Dual Adcs
• Manufacturer: Linear Technology Corporation

APPLICATIONS INFORMATION
LTC2195
LTC2194/LTC2193
Encode Input
The signal quality of the encode inputs strongly affects
the A/D noise performance. The encode inputs should
be treated as analog signals—do not route them next to
digital traces on the circuit board. There are two modes
of operation for the encode inputs: the differential encode
mode (Figure 10), and the single-ended encode mode
(Figure 11).
The differential encode mode is recommended for sinu-
soidal, PECL, or LVDS encode inputs (Figures 12, 13). The
encode inputs are internally biased to 1.2V through 10k
equivalent resistance. The encode inputs can be taken above
V
to 1.6V. In the differential encode mode, ENC
at least 200mV above ground to avoid falsely triggering the
single-ended encode mode. For good jitter performance
ENC
The single-ended encode mode should be used with
CMOS encode inputs. To select this mode, ENC
nected to ground and ENC
20
DD
(up to 3.6V), and the common mode range is from 1.1V
+
should have fast rise and fall times.
ENC
ENC
Figure 10. Equivalent Encode Input Circuit
for Differential Encode Mode
1.8V TO 3.3V
Figure 11. Equivalent Encode Input Circuit
for Single-Ended Encode Mode
+
–
LTC2195
0V
15k
30k
V
DD
ENC
ENC
V
DD
+
+
–
is driven with a square wave
LTC2195
30k
CMOS LOGIC
DIFFERENTIAL
COMPARATOR
BUFFER
219543 F11
–
219543 F10
should stay
–
is con-
encode input. ENC
so 1.8V to 3.3V CMOS logic levels can be used. The ENC
threshold is 0.9V. For good jitter performance ENC
have fast rise and fall times. If the encode signal is turned
off or drops below approximately 500kHz, the A/D enters
nap mode.
Clock PLL and Duty Cycle Stabilizer
The encode clock is multiplied by an internal phase-locked
loop (PLL) to generate the serial digital output data. If the
encode signal changes frequency or is turned off, the PLL
requires 25µs to lock onto the input clock.
A clock duty cycle stabilizer circuit allows the duty cycle
of the applied encode signal to vary from 30% to 70%.
In the serial programming mode it is possible to disable
the duty cycle stabilizer, but this is not recommended. In
the parallel programming mode the duty cycle stabilizer
is always enabled.
0.1µF
0.1µF
Figure 13. PECL or LVDS Encode Drive
T1 = MA/COM ETC1-1-13
RESISTORS AND CAPACITORS
ARE 0402 PACKAGE SIZE
Figure 12. Sinusoidal Encode Drive
PECL OR
CLOCK
LVDS
T1
+
can be taken above V
0.1µF
0.1µF
50Ω
50Ω
ENC
ENC
+
–
0.1µF
100Ω
ENC
ENC
LTC2195
+
–
219543 F13
LTC2195
DD
219543 F12
(up to 3.6V)
+
should
219543p
+