ltc2195 Linear Technology Corporation, ltc2195 Datasheet - Page 23

• Manufacturer Part Number: ltc2195
• Description: Ltc2195/ltc2194/ltc2193 - 16-bit, 125/105/80msps Low Power Dual Adcs
• Manufacturer: Linear Technology Corporation

APPLICATIONS INFORMATION
The first bit of the 16-bit input word is the R/W bit. The
next seven bits are the address of the register (A6:A0).
The final eight bits are the register data (D7:D0).
If the R/W bit is low, the serial data (D7:D0) will be writ-
ten to the register set by the address bits (A6:A0). If the
R/W bit is high, data in the register set by the address bits
(A6:A0) will be read back on the SDO pin (see the Timing
Diagrams). During a read back command the register is
not updated and data on SDI is ignored.
The SDO pin is an open-drain output that pulls to ground
with a 200Ω impedance. If register data is read back
through SDO, an external 2k pull-up resistor is required.
If serial data is only written and read back is not needed,
Table 4. Serial Programming Mode Register Map (PAR/SER = GND)
REGISTER A0: RESET REGISTER (ADDRESS 00h)
REGISTER A1: FORMAT AND POWER-DOWN REGISTER (ADDRESS 01h)
Bit 7
Bits 6-0
Bit 7
Bit 6
Bit 5
Bits 4, 3, 0
Bits 1, 2
DCSOFF
RESET
D7
D7
RESET
0 = Not Used
1 = Software Reset. All Mode Control Registers are Reset to 00h. The ADC is Momentarily Placed in Sleep Mode.
This Bit is Automatically Set Back to Zero After the Reset is Complete
Unused, Don’t Care Bits.
DCSOFF
0 = Clock Duty Cycle Stabilizer On
1 = Clock Duty Cycle Stabilizer Off. This is not recommended.
RAND
0 = Data Output Randomizer Mode Off
1 = Data Output Randomizer Mode On
TWOSCOMP
0 = Offset Binary Data Format
1 = Two’s Complement Data Format
SLEEP:NAP_2:NAP_1
000 = Normal Operation
0X1 = Channel 1 in Nap Mode
01X = Channel 2 in Nap Mode
1XX = Sleep Mode. Both Channels are Disabled.
Note: Any Combination of Channels Can Be Placed in Nap Mode
Unused, Don’t Care Bits
RAND
D6
D6
X
Software Reset Bit
TWOSCOMP
Clock Duty Cycle Stabilizer Bit
Data Output Randomizer Mode Control Bit
Two’s Complement Mode Control Bit
Sleep/Nap Mode Control Bits
D5
D5
X
SLEEP
D4
D4
X
then SDO can be left floating and no pull-up resistor is
needed.
Table 4 shows a map of the mode control registers.
Software Reset
If serial programming is used, the mode control registers
should be programmed as soon as possible after the power
supplies turn on and are stable. The first serial command
must be a software reset which will reset all register data
bits to logic 0. To perform a software reset, bit D7 in the
reset register is written with a logic 1. After the reset is
complete, bit D7 is automatically set back to zero.
NAP_2
D3
D3
X
D2
D2
X
X
LTC2194/LTC2193
D1
D1
X
X
LTC2195
NAP_1
D0
D0
X
23
219543p