sam3s16 ATMEL Corporation, sam3s16 Datasheet - Page 21

• Manufacturer Part Number: sam3s16
• Description: At91sam Arm-based Flash Mcu
• Manufacturer: ATMEL Corporation

7.5
7.6
11117AS–ATARM–12-Jul-11
Master to Slave Access
Peripheral DMA Controller
All the Masters can normally access all the Slaves. However, some paths do not make sense,
for example allowing access from the Cortex-M3 S Bus to the Internal ROM. Thus, these paths
are forbidden or simply not wired and shown as “-” in the following table.
Table 7-3.
The Peripheral DMA Controller handles transfer requests from the channel according to the fol-
lowing priorities (Low to High priorities):
Table 7-4.
• Handles data transfer between peripherals and memories
• Low bus arbitration overhead
• Next Pointer management for reducing interrupt latency requirement
Instance Name
Slaves
0
1
2
3
4
USART1
USART0
UART1
UART0
UART1
HSMCI
– One Master Clock cycle needed for a transfer from memory to peripheral
– Two Master Clock cycles needed for a transfer from peripheral to memory
PWM
TWI1
TWI0
PIOA
TWI1
TWI0
DAC
SSC
SPI
SAM3S16 Master to Slave Access
Peripheral DMA Controller
External Bus Interface
Channel T/R
Peripheral Bridge
Internal SRAM
Internal Flash
Internal ROM
Transmit
Transmit
Transmit
Transmit
Transmit
Transmit
Transmit
Transmit
Transmit
Transmit
Transmit
Transmit
Receive
Receive
Receive
Masters
100 Pins
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Cortex-M3 I/D
Bus
X
X
0
-
-
-
SAM3S16 Preliminary
Cortex-M3 S
Bus
X
X
X
1
-
-
PDC
X
X
X
X
2
-
CRCCU
X
X
X
X
3
-
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