ad73322l Analog Devices, Inc., ad73322l Datasheet - Page 21

• Manufacturer Part Number: ad73322l
• Description: Low Cost, Low Power Cmos General-purpose Dual Analog Front End
• Manufacturer: Analog Devices, Inc.

CONTROL REGISTER A
Table 18. Control Register A Description
7
RESET
Bit
0
1
2
3
4
5
6
7
CONTROL REGISTER B
Table 19. Control Register B Description
7
CEE
Bit
0
1
2
3
4
5
6
7
CONTROL REGISTER C
Table 20. Control Register C Description
7
—
Bit
0
1
2
3
4
5
6
7
Name
PU
PUAGT
PUIA
PUADC
PUDAC
PUREF
RU
—
Name
DATA/PGM
MM
DLB
SLB
DC0
DC1
DC2
RESET
6
MCD2
Name
DIR0
DIR1
SCD0
SCD1
MCD0
MCD1
MCD2
CEE
6
RU
6
DC2
MCD1
5
Description
Power-Up Device (0 = power-down; 1 = power on)
Analog Gain Tap Power (0 = power-down; 1 = power on)
Input Amplifier Power (0 = power-down; 1 = power on)
ADC Power (0 = power-down; 1 = power on)
DAC Power (0 = power-down; 1 = power on)
REF Power (0 = power-down; 1 = power on)
REFOUT Use (0 = disable REFOUT; 1 = enable REFOUT)
Reserved, must be programmed to 0
Description
Decimation/Interpolation Rate (Bit 0)
Decimation/Interpolation Rate (Bit 1)
Serial Clock Divider (Bit 0)
Serial Clock Divider (Bit 1)
Master Clock Divider (Bit 0)
Master Clock Divider (Bit 1)
Master Clock Divider (Bit 2)
Control Echo Enable (0 = off; 1 = enabled)
5
DC1
5
PUREF
Description
Operating Mode (0 = program; 1 = data mode)
Mixed Mode (0 = off; 1 = enabled)
Digital Loop-Back Mode (0 = off; 1 = enabled)
SPORT Loop-Back Mode (0 = off; 1 = enabled)
Device Count (Bit 0)
Device Count (Bit 1)
Device Count (Bit 2)
Software Reset (0 = off; 1 = initiates reset)
4
MCD0
4
DC0
4
PUDAC
Rev. A | Page 21 of 48
3
SLB
3
SCD1
3
PUADC
2
BLB
2
SCD0
2
PUIA
1
MM
1
DIR1
1
PUAGT
0
DATA/PGM
AD73322L
0
PU
0
DIR0