ad73322l Analog Devices, Inc., ad73322l Datasheet - Page 7

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ad73322l

Manufacturer Part Number
ad73322l
Description
Low Cost, Low Power Cmos General-purpose Dual Analog Front End
Manufacturer
Analog Devices, Inc.
Datasheet

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SIGNAL RANGES
Table 3.
Mnemoic
VREFCAP
VREFOUT
ADC
DAC
TIMING CHARACTERISTICS
AVDD = 3 V ± 10%; DVDD = 3 V ± 10%; AGND = DGND = 0 V; T
Table 4.
Parameter
Clock Signals
Serial Port
t
t
t
t
t
t
t
t
t
t
t
t
t
1
2
3
4
5
6
7
8
9
10
11
12
13
Description
Maximum input range at V
Nominal reference level
Maximum voltage output swing
Nominal voltage output swing
Output bias voltage
Single-Ended
Differential
Single-Ended
Differential
Limit at T
61
24.4
24.4
t
0.4 × t
0.4 × t
20
0
10
10
10
10
30
1
1
1
A
= −40°C to +105°C
IN
Rev. A | Page 7 of 48
A
= T
ns min
ns min
ns min
ns max
ns min
ns min
ns max
Unit
ns min
ns min
ns min
ns min
ns min
ns max
MlN
to T
MAX
, unless otherwise noted.
Description
See Figure 2
MCLK period
MCLK width high
MCLK width low
See Figure 4 and Figure 5
SCLK period
SCLK width high
SCLK width low
SDI/SDIFS setup before SCLK low
SDI/SDIFS hold after SCLK low
SDOFS delay from SCLK high
SDOFS hold after SCLK high
SDO hold after SCLK high
SDO delay from SCLK high
SCLK delay from MCLK
1.2 V ± 10%
1.2 V ± 10%
1.578 V p-p
1.578 V p-p
3.156 V p-p
1.0954 V p-p
2.1909 V p-p
Range
1.0954 V p-p
VREFOUT
AD73322L

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