ad73311 Analog Devices, Inc., ad73311 Datasheet - Page 22

• Manufacturer Part Number: ad73311
• Description: Low Cost, Low Power Cmos General Purpose Analog Front End
• Manufacturer: Analog Devices, Inc.

Control Register A contains a 3-bit field (DC0–2) that is pro-
grammed by the DSP during the programming phase. The default
condition is that the field contains 000b, which is equivalent to
a single device in cascade (see Table XVII). However, for
cascade operation this field must contain a binary value that is
one less than the number of devices in the cascade.
DC2
0
0
0
0
1
1
1
1
PERFORMANCE
As the AD73311 is designed to provide high performance, low
cost conversion, it is important to understand the means by
which this high performance can be achieved in a typical applica-
tion. This section will, by means of spectral graphs, outline the
typical performance of the device and highlight some of the
options available to users in achieving their desired sample
rate, either directly in the device or by doing some post-processing
in the DSP, while also showing the advantages and disadvan-
tages of the different approaches.
Encoder Section
The encoder section samples at DMCLK/256, which gives a
64 kHz output rate for DMCLK equal to 16.384 MHz. The
noise shaping of the sigma-delta modulator also depends on the
frequency at which it is clocked, which means that the best
dynamic performance in a particular bandwidth is achieved by
oversampling at the highest possible rate. If we assume that the
signals of interest are in the voice bandwidth of dc–4 kHz, then
sampling at 64 kHz gives a spectral response which ensures good
SNR performance in the voice bandwidth, as shown in Figure 14.
AD73311
–100
–150
–60
0
0
Table XVII. Device Count Settings
DC1
0
0
1
1
0
0
1
1
5
10
FREQUENCY – kHz
DC0
0
1
0
1
0
1
0
1
15
20
S/N+D = 59.4951
25
Cascade Length
1
2
3
4
5
6
7
8
30
32
If sampling at 8 kHz is required, the user must implement some
post-processing in the DSP engine to band limit the signal and
decimate the samples to achieve the ultimate sampling rate of
8 kHz. Figure 15 shows the final spectral response of the
64 kHz sampled data having been digitally filtered and deci-
mated to an 8 kHz rate. The filter used was a 6th order ellip-
tical filter.
The device features an on-chip master clock divider circuit that
allows the sample rate to be reduced. The present choice of
clock divider options permits the device to sample at 64 kHz,
32 kHz, 21.33 kHz, 16 kHz and 12.8 kHz from a 16.384 MHz
master clock. Reducing the DMCLK rate lowers the sampling
rate of the sigma-delta modulator, which causes the noise shaping
to occur in a reduced bandwidth. The SNR performance up to
F
but will be disimproved in the voice bandwidth due to the re-
duced noise shaping. Figure 16 shows this effect for a sampling
rate of 16 kHz.
S
/2 will still be similar to that in the case of 64 kHz sampling,
–100
–120
–140
–100
–120
–140
–20
–40
–60
–80
–20
–40
–60
–80
0
0
0
0
0.5
1
1.0
2
1.5
FREQUENCY – kHz
FREQUENCY – kHz
3
2.0
4
2.5
5
S/N+D = 80.615918
S/N+D = 59.162677
3.0
6
3.5
7
4.0
8