ics83940ay-02 Integrated Device Technology, ics83940ay-02 Datasheet
ics83940ay-02
Manufacturer Part Number
ics83940ay-02
Description
Differential/lvcmos-input Lvcmos-output 1 18 200-mhz Clock Buffer
Manufacturer
Integrated Device Technology
Datasheet
1.ICS83940AY-02.pdf
(14 pages)
Available stocks
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Company:
Part Number:
ics83940ay-02LF
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
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Part Number:
ics83940ay-02LFT
Manufacturer:
IDT, Integrated Device Technology Inc
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G
standard differential input levels. The single ended clock in-
put accepts LVCMOS or LVTTL input levels.The low imped-
ance LVCMOS/LVTTL outputs are designed to drive 50Ω
series or parallel terminated transmission lines. The effective
fanout can be increased from 18 to 36 by utilizing the ability
of the outputs to drive two series terminated lines.
The ICS83940-02 is characterized at full 3.3V, full 2.5V and
mixed 3.3V input and 2.5V output operating supply modes.
Guaranteed output and part-to-part skew characteristics
make the ICS83940 ideal for those clock distribution applica-
tions demanding well defined performance and repeatability.
B
83940AY-02
HiPerClockS™
ICS
LVCMOS_CLK
LOCK
ENERAL
CLK_SEL
nCLK0
CLK0
D
The ICS83940-02 is a low skew, 1-to-18 Fanout
Buffer and a member of the HiPerClock S ™
family of High Performance Clock Solutions from
ICS. The 83940-02 has two selectable clock in-
puts. The CLK0, nCLK0 pair can accept most
IAGRAM
D
ESCRIPTION
0
1
www.icst.com/products/hiperclocks.html
D
Q0:Q17
IFFERENTIAL
1
P
LVCMOS_CLK
F
• 18 LVCMOS/LVTTL outputs, 7Ω typical output impedance
• Selectable LVCMOS_Clock or CLK0, nCLK0 input pair
• LVCMOS_CLK supports the following input types:
• CLK0, nCLK0 pair can accept the following differential
• Maximum output frequency: 200MHz
• Output skew: 120ps (maximum)
• Part-to-part skew: 850ps (maximum)
• Output supply modes:
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
• Pin compatible with the MPC940L in single supply
IN
LVCMOS or LVTTL
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
Core/Output
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V
applications
EATURES
CLK_SEL
-
A
TO
GND
GND
nCLK
V
CLK
V
DDO
SSIGNMENT
DD
-LVCMOS/LVTTL F
7mm x 7mm x 1.4mm package body
1
2
3
4
5
6
7
8
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
ICS83940-02
32-Lead LQFP
Y Pacakge
Top View
L
ICS83940-02
OW
S
ANOUT
KEW
24
23
22
21
20
19
18
17
REV. A JULY 30, 2007
, 1-
Q6
Q7
Q8
V
Q9
Q10
Q11
GND
DDO
B
TO
UFFER
-18
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