ics9lprs535 Integrated Device Technology, ics9lprs535 Datasheet - Page 3

• Manufacturer Part Number: ics9lprs535
• Description: Integrated Circuit Systems, Inc.
• Manufacturer: Integrated Device Technology

SSOP/TSSOP Pin Description (Continued)
1461A—07/28/09
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PCI_STOP#/SRCT5_LPR
VDDSRC
GNDSRC
SRCC7_LPR/CR#_E
SRCT7_LPR/CR#_F
VDDSRC_IO
CPUC2_ITP_LPR/SRCC8_LPR OUT
CPUT2_ITP_LPR/SRCT8_LPR OUT
VDDCPU_IO
CPUC1_LPR_F
CPUT1_LPR_F
GNDCPU
CPUC0_LPR
CPUT0_LPR
VDDCPU
CK_PWRGD/PD#
FSLB/TEST_MODE
GNDREF
X2
X1
VDDREF
REF0/FSLC/TEST_SEL
SDATA
SCLK
Integrated
Circuit
Systems, Inc.
PWR Supply for SRC clocks, 3.3V nominal
PWR Ground pin for the SRC outputs
PWR 1.05V to 3.3V from external power supply
PWR 1.05V to 3.3V from external power supply
OUT
OUT
PWR Ground pin for the CPU outputs
OUT
OUT
PWR Supply for CPU clocks, 3.3V nominal
PWR Ground pin for the REF outputs.
OUT Crystal output, Nominally 14.318MHz
PWR Ref, XTAL power supply, nominal 3.3V
I/O
I/O
I/O
I/O
I/O
IN
IN
IN
IN
Stops all PCICLKs at logic 0 level, when low. Can also stop SRC clocks. Free running PCICLKs are not effected by this
input. / True clock of push-pull SRC pair with int. 33ohm series resistor.
Complementary clock of push-pull SRC output with int. 33ohm series resistor/CR#_E input. Disable SRC7 via Byte 3, bit 3
before using as CR#_E.
Byte 6, bit 7: 0=SRC7 (default), 1=CR#_E
Outputs controlled by CR#_E are not present on this device
True clock of push-pull SRC output with int. 33 ohm series resistor/CR#_F input. Disable SRC7 via Byte 3, bit 3 before
using CR#_F.
Byte 6, bit 6: 0 = SRC7 (default),1 = CR#_F enabled to control SRC8.
Complementary clock of low power differential CPU2_ITP/SRC pair. No Rs needed. The function of this pin is determined
by the latched input value on pin 7, PCIF5/ITP_EN on powerup. The function is as follows:
Pin 7 latched input Value
0 = SRC8#
1 = ITP#
True clock of low power differential CPU2_ITP/SRC8 pair. No Rs needed. The function of this pin is determined by the
latched input value on pin 7, PCIF5/ITP_EN on powerup. The function is as follows:
Pin 7 latched input Value
0 = SRC8
1 = ITP
Complementary clock of differential pair 0.8V push-pull CPU outputs with integrated 33ohm series resistor. Free running
during iAMT. No 50ohm resistor to GND needed.
True clock of differential pair 0.8V push-pull CPU outputs with integrated 33ohm series resistor. Free running during
iAMT No 50 ohm resistor to GND needed.
Complementary clock of differential pair 0.8V push-pull CPU outputs with integrated 33ohm series resistor. No 50 ohm
resistor to GND needed.
True clock of differential pair 0.8V push-pull CPU outputs with integrated 33ohm series resistor. No 50 ohm resistor to
GND needed.
Notifies CK505 to sample latched inputs, or iAMT entry/exit, or PWRDWN# mode
TEST_MODE is a real time input to select between Hi-Z and REF/N divider mode while in test mode. Refer to Test
Clarification Table.
Crystal input, Nominally 14.318MHz.
14.318 MHz reference clock./ 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for
Vil_FS and Vih_FS values. /TEST_Sel: 3-level latched input to enable test mode. Refer to Test Clarification Table
Data pin for SMBus circuitry, 3.3V tolerant.
Clock pin of SMBus circuitry, 5V tolerant.
3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values.
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ICS9LPRS535
Datasheet