ics9lprs365 Integrated Device Technology, ics9lprs365 Datasheet - Page 13

• Manufacturer Part Number: ics9lprs365
• Description: 64-pin Ck505 W/fully Integrated Voltage Regulator + Integrated Series Resistor
• Manufacturer: Integrated Device Technology

1218—09/01/10
1
1
2
1
2
3
4
5
CLK and falling edge of CLK#.
*T
Electrical Characteristics - SMBus Interface
AC Electrical Characteristics - Input/Common Parameters
AC Electrical Characteristics - Low Power Differential Outputs
Guaranteed by design and characterization, not 100% tested in production.
Guaranteed by design and characterization, not 100% tested in production.
Guaranteed by design and characterization, not 100% tested in production.
Optional. Only applies when PCI_STOP# and/or CPU_STOP# is present.
Slew rate measured through Vswing centered around differential zero
Vxabs is defined as the voltage where CLK = CLK#
Only applies to the differential rising edge (CLK rising and CLK# falling)
Defined as the total variation of all crossing voltages of CLK rising and CLK# falling. Matching applies to rising edge rate of
A
Maximum SMBus Operating
CPU Jitter - Cycle to Cycle
SRC Jitter - Cycle to Cycle
DOT Jitter - Cycle to Cycle
= 0 - 70°C; V
Maximum Output Voltage
Differential Voltage Swing
Low-level Output Voltage
Minimum Output Voltage
Crossing Point Variation
Falling Edge Slew Rate
Rising Edge Slew Rate
Crossing Point Voltage
Clock/Data Rise Time
Clock/Data Fall Time
CPU[2_ITP:0] Skew
Slew Rate Variation
Current sinking at
SRC[10:0] Skew
Clk Stabilization
CPU[1:0] Skew
SMBus Voltage
PARAMETER
V
SCLK/SDATA
PARAMETER
PARAMETER
SCLK/SDATA
Tdrive_SRC
Tdrive_CPU
Tdrive_PD#
OLSMB
Duty Cycle
Frequency
Trise_PD#
Tfall_PD#
DD
= 0.4 V
= 3.3 V +/-5%; C
L
=5pF, R
CPU
CPU
SYMBOL
SYMBOL
SYMBOL
SRC
CPUJ
SRCJ
DOTJ
V
V
F
T
T
V
I
T
t
V
XABSVAR
T
PULLUP
T
T
V
V
D
T
T
SLVAR
OLSMB
SMBUS
DRSRC
DRSRC
t
SWING
V
t
DRPD
XABS
STAB
SLR
FALL
RISE
FLR
HIGH
LOW
RI2C
FI2C
CYC
SKEW10
SKEW20
S
DD
SKEW
=22Ω (unless specified otherwise.)
C2C
C2C
C2C
Fall/rise time of PD#, PCI_STOP#
Differential output enable after
assertion of PD# to 1st clock
From VDD Power-Up or de-
CPU_STOP# de-assertion
Single-ended Measurement
Single-ended Measurement
Single-ended Measurement
PCI_STOP# de-assertion
Differential Measurement
Differential Measurement
Differential Measurement
Differential Measurement
Differential Measurement
Differential Measurement
Differential Measurement
Differential Measurement
Differential Measurement
Differential Measurement
CPU output enable after
and CPU_STOP# inputs
SRC output enable after
Includes undershoot
Includes overshoot
(Max VIL - 0.15) to
(Min VIH + 0.15) to
PD# de-assertion
(Min VIH + 0.15)
(Max VIL - 0.15)
CONDITIONS
CONDITIONS
CONDITIONS
SMB Data Pin
Block Mode
@ I
13
PULLUP
-300
MIN
MIN
MIN
300
300
2.7
2.5
2.5
45
4
ICS9LPRS365
1150
MAX
1000
MAX
MAX
TBD
300
550
140
125
250
100
150
300
100
5.5
0.4
1.8
15
10
20
55
85
5
5
8
8
Datasheet
UNITS
UNITS
UNITS
V/ns
V/ns
kHz
mV
mV
mV
mV
mV
mA
ms
ns
us
ns
ns
ns
ps
ps
ps
ps
ps
ps
ns
ns
%
%
V
V
NOTES
Notes
Notes
1,3,4
1,3,5
1,2
1,2
1,2
1,2
1,2
1,2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1