ics9lprs365 Integrated Device Technology, ics9lprs365 Datasheet - Page 9

• Manufacturer Part Number: ics9lprs365
• Description: 64-pin Ck505 W/fully Integrated Voltage Regulator + Integrated Series Resistor
• Manufacturer: Integrated Device Technology

MLF Pin Description (Continued)
1218—09/01/10
PIN #
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
VDDSRC_IO
SRCT4
SRCC4
GNDSRC
SRCT9
SRCC9
SRCC11/CR#_G
SRCT11/CR#_H
SRCT10
SRCC10
VDDSRC_IO
CPU_STOP#
PCI_STOP#
VDDSRC
SRCC6
SRCT6
PIN NAME
TYPE
PWR
PWR
OUT
OUT
OUT
OUT
PWR
PWR
OUT
OUT
I/O
I/O
I/O
I/O
IN
IN
DESCRIPTION
True clock of differential SRC clock pair 4
Complement clock of differential SRC clock pair 4
Ground pin for SRC clocks.
True clock of differential SRC clock pair.
Complement clock of differential SRC clock pair.
SRC11 complement /Clock Request control for SRC9 pair
The power-up default is SRC11#, but this pin may also be used as a Clock Request control of
SRC9 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC11 output pair
must first be disabled in byte 3, bit 7 of SMBus configuration space After the SRC11 output is
disabled (high-Z), the pin can then be set to serve as a Clock Request for SRC9 pair using byte
6, bit 5 of SMBus configuration space
Byte 6, bit 5
0 = SRC11# enabled (default)
1= CR#_G controls SRC9
SRC11 true or Clock Request control H for SRC10 pair
The power-up default is SRC11, but this pin may also be used as a Clock Request control of
SRC10 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC11 output pair
must first be disabled in byte 3, bit 7 of SMBus configuration space After the SRC11 output is
disabled (high-Z), the pin can then be set to serve as a Clock Request for SRC10 pair using
byte 6, bit 4 of SMBus configuration space
Byte 6, bit 4
0 = SRC11 enabled (default)
1= CR#_H controls SRC10.
True clock of differential SRC clock pair.
Complement clock of differential SRC clock pair.
Stops all CPU Clocks, except those set to be free running clocks. In AMT mode 3 bits are
shifted in from the ICH to set the FSC, FSB, FSA values
Stops all PCI Clocks, except those set to be free running clocks. In AMT mode 3 bits are shifted
in from the ICH to set the FSC, FSB, FSA values
VDD pin for SRC Pre-drivers, 3.3V nominal
Complement clock of low power differential SRC clock pair.
True clock of low power differential SRC clock pair.
1.05V to 3.3V from external power supply
1.05V to 3.3V from external power supply
9
ICS9LPRS365
Datasheet