ics9lprs365 Integrated Device Technology, ics9lprs365 Datasheet - Page 14

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ics9lprs365

Manufacturer Part Number
ics9lprs365
Description
64-pin Ck505 W/fully Integrated Voltage Regulator + Integrated Series Resistor
Manufacturer
Integrated Device Technology
Datasheet

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Intentional PCI Clock to Clock Delay
1218—09/01/10
1
2
3
*T
Electrical Characteristics - PCICLK/PCICLK_F
Guaranteed by design and characterization, not 100% tested in production.
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
See PCI Clock-to-Clock Delay Figure
A
= 0 - 70°C; V
Intentional PCI-PCI delay
Absolute min/max period
Falling Edge Slew Rate
Rising Edge Slew Rate
Jitter, Cycle to cycle
Output High Current
Output High Voltage
Output Low Current
Output Low Voltage
Long Accuracy
PARAMETER
Clock period
Duty Cycle
Skew
DD
= 3.3 V +/-5%
SYMBOL
PCI_F5
t
T
jcyc-cyc
t
ppm
t
T
t
V
V
t
delay
I
skew
period
I
SLR
d
FLR
OH
PCI0
PCI4
OL
PCI1
PCI2
abs
PCI3
OH
OL
t1
200 ps nominal steps
33.33MHz output nominal/spread
see Tperiod min-max values
Measured from 0.8 to 2.0 V
Measured from 2.0 to 0.8 V
33.33MHz output nominal
33.33MHz output spread
V
V
V
V
OH
OL
OL
OH
CONDITIONS
@MAX = 3.135 V
1.0ns
@ MIN = 1.95 V
@ MAX = 0.4 V
I
I
OH
@MIN = 1.0 V
V
V
V
V
OL
T
T
T
T
14
= -1 mA
= 1 mA
= 1.5 V
= 1.5 V
= 1.5 V
= 1.5 V
29.99100
29.49100
-300
MIN
-33
2.4
30
45
1
1
200 nominal
30.00900
30.15980
30.65980
ICS9LPRS365
MAX
300
-33
250
500
0.4
38
55
4
4
Datasheet
UNITS
V/ns
V/ns
ppm
mA
mA
mA
mA
ns
ns
ns
ps
ps
ps
%
V
V
NOTES
1,2
1,3
2
2
2
1
1
1
1
1
1
1
1
1
1
1

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