ics527-03 Integrated Device Technology, ics527-03 Datasheet - Page 2

• Manufacturer Part Number: ics527-03
• Description: Clock Slicer User Configurable Pecl Output Zero Delay Buffer
• Manufacturer: Integrated Device Technology

IDT™ / ICS™ CLOCK SLICER USER CONFIGURABLE PECL OUTPUT ZDB 2
ICS527-03
CLOCK SLICER USER CONFIGURABLE PECL OUTPUT ZDB
Pin Assignment
Pin Descriptions
1,2, 24-28
FBPECL
FBPECL
Number
CLKIN
PDTS
12-18
6, 23
9, 20
DIV2
GND
VDD
Pin
4, 5
10
11
19
21
22
R5
R6
S0
S1
3
7
8
F0
F1
F2
28 pin 150 mil body SSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
R5, R6,
FPECL
FPECL
Name
S0, S1
CLKIN
R0-R4
PDTS
F0-F6
PECL
PECL
DIV2
GND
VDD
RES
Pin
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Output
Output
Power
Power
Type
Input
Input
Input
Input
Input
Input
Input
Input
BIAS
Pin
R4
R3
R2
R1
R0
VDD
PECL
PECL
GND
RES
F6
F5
F4
F3
Reference divider word input pins determined by user. Forms a binary number
from 0 to 127. Internal pull-up.
Selects CLK2 function to output a SYNC signal or a divide by 2 of CLK1 based
on the table above. Internal pull-up.
Select pins for output divider determined by user. See table above. Internal
pull-up.
Connect to +3.3 V.
PECL feedback input.
Complementary PECL feedback input.
Connect to ground
Clock input.
Power Down. Active low. Turns off entire chip when low, both clock outputs are
tri-stated. Internal pull-up.
Feedback divider word input pins determined by user. Forms a binary number
from 0 to 127. Internal pull-up
Resistor connection to VDD for setting level of PECL outputs.
Complementary PECL input clock.
PECL input clock.
Output Frequency and Output
Divider Table
S1 S0
0
0
1
1
0
1
0
1
Output Divider
Pin Description
2
4
8
1
PECL ZDB AND MULTIPLIER/DIVIDER
Output Frequency (MHz)
ICS527-03
2.5 - 20
20 -160
10 - 80
5 - 40
REV D 092209