ics527-02 Integrated Device Technology, ics527-02 Datasheet

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ics527-02

Manufacturer Part Number
ics527-02
Description
Clock Slicer User Configurable Pecl Input Zero Delay Buffer
Manufacturer
Integrated Device Technology
Datasheet
CLOCK SLICER USER CONFIGURABLE PECL INPUT ZERO DELAY BUFFER
IDT™ / ICS™ CLOCK SLICER USER CONFIGURABLE PECL INPUT ZERO DELAY BUFFER 1
Description
The ICS527-02 Clock Slicer is the most flexible way to
generate a CMOS output clock from a PECL input
clock with zero skew. The user can easily configure the
device to produce nearly any output clock that is
multiplied or divided from the input clock. The part
supports non-integer multiplications and divisions. A
SYNC pulse indicates when the rising clock edges are
aligned with zero skew. Using Phase-Locked Loop
(PLL) techniques, the device accepts an input clock up
to 200 MHz and produces an output clock up to 160
MHz.
The ICS527-02 aligns rising edges on PECLIN with
FBIN at a ratio determined by the reference and
feedback dividers.
For a PECL input and output clock with zero delay, use
the ICS527-04.
For a CMOS input and PECL output with zero delay,
use the ICS527-03.
Block Diagram
PECLIN
PECLIN
FBIN
Reference
Feedback
R6:R0
Divider
Divider
F6:F0
7
7
2
Phase Comparator,
Charge Pump, and
GND
Loop Filter
2
PDTS
VDD
VCO
SYNC
Features
NOTE: EOL for non-green parts to occur on
5/13/10 per PDN U-09-01
Packaged as 28-pin SSOP (150 mil body)
Synchronizes fractional clocks rising edges
PECL IN to CMOS OUT
Pin selectable dividers
Zero input to output skew
User determines the output frequency—no software
needed
Slices frequency or period
Input clock frequency of 1.5 MHz to 200 MHz
Output clock frequencies from 4 MHz to 160 MHz
Very low jitter
Duty cycle of 45/55
Operating voltage of 3.3 V
Advanced, low-power CMOS process
Industrial temperature version available
Divider
S1:S0
Output
2
Divide
by 2
DIV2
1
0
ICS527-02
33 ohm
33 ohm
DATASHEET
ICS527-02
Feedback can
come from
CLK1 or CLK2
(not both)
REV H 092209
CLK1
CLK2

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ics527-02 Summary of contents

Page 1

... CLOCK SLICER USER CONFIGURABLE PECL INPUT ZERO DELAY BUFFER Description The ICS527-02 Clock Slicer is the most flexible way to generate a CMOS output clock from a PECL input clock with zero skew. The user can easily configure the device to produce nearly any output clock that is multiplied or divided from the input clock ...

Page 2

... Output clock 2. Can be SYNC pulse or a low skew divide CLK1. Output Output clock 1. PECL ZDB AND MULTIPLIER/DIVIDER Output Frequency (MHz) Commercial Industrial -160 32 - 140 DIV2 CLK2 SYNC 1 CLK1/2 Pin Description ICS527-02 REV H 092209 ...

Page 3

... CLOCK SLICER USER CONFIGURABLE PECL INPUT ZERO DELAY BUFFER External Components Decoupling Capacitors As with any high performance mixed-signal IC, the ICS527-02 must be isolated from system power supply noise to perform optimally. Decoupling capacitors of 0.01µF must be connected between each VDD and the PCB ground plane. The capacitor must be connected close to the device to minimize lead inductance ...

Page 4

... Printed Circuit Board layout, so the ICS527-02 automatically produces the correct clock when mounted on the board also possible to connect the inputs to parallel I/O ports in order to switch frequencies. The output of the ICS527-02 can be determined by the following simple equation: FB Frequency = Input Frequency ...

Page 5

... An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers. Other signal traces should be routed away from the ICS527-02. This includes signal traces just underneath the device layers adjacent to the ground plane layer used by the device. ...

Page 6

... CLOCK SLICER USER CONFIGURABLE PECL INPUT ZERO DELAY BUFFER Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the ICS527-02. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied ...

Page 7

... Common PECLIN measured at FBIN PECL ZDB AND MULTIPLIER/DIVIDER Min. Typ. Max. Units 5 pF ±70 mA 270 k Min. Typ. Max. Units 1.5 200 MHz 4 160 MHz 4 140 MHz ± -250 250 ps 0 500 ps ICS527-02 REV H 092209 ...

Page 8

... SSOP, .150 mil Body, 0.025 mm Pitch) Millimeters Min Max Min A 1.35 1.75 .053 A1 0.10 0.25 .0040 0.20 0.30 .008 C 0.18 0.25 .007 D 9.80 10.00 .386 E 5.80 6.20 .228 E1 3.80 4.00 .150 e 0.635 Basic 0.025 Basic L 0.40 1.27 .016 aaa -- 0. ICS527-02 Inches Max .069 .010 .059 .012 .010 .394 .244 .157 .050 8 0.004 c REV H 092209 ...

Page 9

... PECL ZDB AND MULTIPLIER/DIVIDER Package Temperature 28-pin SSOP 0 to +70 C 28-pin SSOP 0 to +70 C 28-pin SSOP -40 to +85 C 28-pin SSOP -40 to +85 C 28-pin SSOP 0 to +70 C 28-pin SSOP 0 to +70 C 28-pin SSOP -40 to +85 C 28-pin SSOP -40 to +85 C ICS527-02 REV H 092209 ...

Page 10

... ICS527-02 CLOCK SLICER USER CONFIGURABLE PECL INPUT ZERO DELAY BUFFER Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 Corporate Headquarters Integrated Device Technology, Inc. www.idt.com © 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc ...

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