ics527-02 Integrated Device Technology, ics527-02 Datasheet - Page 4

• Manufacturer Part Number: ics527-02
• Description: Clock Slicer User Configurable Pecl Input Zero Delay Buffer
• Manufacturer: Integrated Device Technology

IDT™ / ICS™ CLOCK SLICER USER CONFIGURABLE PECL INPUT ZERO DELAY BUFFER 4
ICS527-02
CLOCK SLICER USER CONFIGURABLE PECL INPUT ZERO DELAY BUFFER
because of internal pull-ups) during Printed Circuit
Board layout, so the ICS527-02 automatically produces
the correct clock when mounted on the board. It is also
possible to connect the inputs to parallel I/O ports in
order to switch frequencies.
The output of the ICS527-02 can be determined by the
following simple equation:
Also, the following operating ranges should be
observed:
Typical Example
The layout diagram below will produce the waveforms shown on the right.
Note: The series termination resistor is located before the feedback trace.
40 MHz
40 MHz
Where:
300kHz
FB Frequency
VDD
0.01 F
Reference Divider Word (RDW) = 0 to 127
Feedback Divider Word (FDW) = 0 to 127
FB Frequency is the same as either CLK1 or
CLK2 depending on feedback connection
Input Frequency
------------------------------------------ -
RDW
R5
R6
DIV2
S0
S1
VDD
PECLIN
PECLIN
GND
OECLK2
F0
F1
F2
F3
=
+
Input Frequency
2
CLK1
CLK2
PDTS
FBIN
GND
VDD
R4
R3
R2
R1
R0
F6
F5
F4
20 MHz
33
33
0.01 F
----------------------- -
RDW
FDW
+
+
2
2
50 MHz
SYNC
50 MHz
PECLIN
40 MHz
PECLIN
SYNC
CLK1
CLK2
S0 and S1 should be selected depending on the
frequency of CLK1. The table on page 2 gives the
ranges.
The dividers are expressed as integers. For example, if
a 50 MHz output on CLK1 is desired from a 40 MHz
input, the reference divider word (RDW) should be 2
and the feedback divider word (FDW) should be 3 which
gives the required 5/4 multiplication. If multiple choices
of dividers are available, then the lowest numbers
should be used. In this example, the output divide (OD)
should be selected to be 2. Then R6:R0 is 0000010,
F6:F0 is 0000011 and S1:S0 is 00. Also, this example
assumes CLK1 is connected to FBIN.
If you need assistance determining the optimum divider
settings, please send an e-mail to
[e-mail] with the desired input clock and
the desired output frequency.
PECL ZDB AND MULTIPLIER/DIVIDER
ICS527-02
REV H 092209