ics527-03 Integrated Device Technology, ics527-03 Datasheet - Page 5

• Manufacturer Part Number: ics527-03
• Description: Clock Slicer User Configurable Pecl Output Zero Delay Buffer
• Manufacturer: Integrated Device Technology

IDT™ / ICS™ CLOCK SLICER USER CONFIGURABLE PECL OUTPUT ZDB 5
ICS527-03
CLOCK SLICER USER CONFIGURABLE PECL OUTPUT ZDB
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
1) Each 0.01µF decoupling capacitor should be
mounted on the component side of the board as close
to the VDD pin as possible. No via’s should be used
between decoupling capacitor and VDD pin. The PCB
trace to VDD pin should be kept as short as possible, as
should the PCB trace to the ground via.
2) PECL termination networks should be located as
close to the outputs as possible.
3) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers. Other signal traces should be routed away
from the ICS527-03. This includes signal traces just
underneath the device, or on layers adjacent to the
ground plane layer used by the device.
PECL ZDB AND MULTIPLIER/DIVIDER
ICS527-03
REV D 092209