ics650-01 Integrated Device Technology, ics650-01 Datasheet - Page 2

• Manufacturer Part Number: ics650-01
• Description: System Peripheral Clock Source
• Manufacturer: Integrated Device Technology

MDS 650-01 C
Integrated Circuit Systems • 525 Race Street • San Jose •CA•95126• [phone]tel • [phone]fax
Pin Assignment
Key: I = Input; XO/XI = crystal connections; O = output; P = power supply connection
X1/ICLK
Pin Descriptions
PCLK4
Pin #
UCLK
ACLK
VDD
10
11
12
13
14
15
16
17
18
19
20
USEL
VDD
GND
1
2
3
4
5
6
8
9
7
20M
X2
20 pin (150 mil) SSOP
X1/ICLK
14.318M
PCLK4
PCLK1
PCLK3
PCLK2
2
10
UCLK
PSEL0
PSEL1
1
3
4
7
8
9
Name
USEL
ACLK
5
6
VDD
VDD
GND
GND
ASEL
VDD
20M
OE
X2
Type
16
15
14
13
12
11
17
XO
20
19
18
XI
O
O
O
O
O
O
O
O
P
P
P
P
P
I
I
I
I
I
14.31818 MHz buffered reference clock output.
PSEL1
PSEL0
PCLK2
PCLK3
VDD
GND
Description
UCLK Select pin. Determines frequency of USB clock per table above.
Crystal connection. Connect to parallel mode 14.31818 MHz crystal. Leave open for clock.
Crystal connection. Connect to parallel mode 14.31818 MHz crystal, or clock.
Connect to VDD. Must be same value as other VDD. Decouple with pin 6.
Connect to VDD. Must be same value as other VDD.
Connect to ground.
USB clock output per table above.
Fixed 20 MHz output for Ethernet. Only clock that runs when PSEL1=PSEL0=1.
AC97 Audio clock output per table above.
PCLK output number 4 per table above.
Output Enable. Tri-states all outputs when low.
PCLK output number 1 per table above.
Connect to ground.
ACLK Select pin. Determines frequency of Audio clock per table above.
Connect to VDD. Must be same value as other VDD. Decouple with pin 14.
PCLK output number 3 per table above.
PCLK output number 2 per table above.
Processor Select pin #0. Determines frequencies on PCLKs 1-4 per table above.
Processor Select pin #1. Determines frequencies on PCLKs 1-4 per table above.
ASEL
14.318M
PCLK1
OE
2
Processor Clock (MHz)
Audio Clock (MHz)
0 = connect directly to ground, 1 = connect directly
to VDD, M=leave unconnected (floating)
PSEL1 PSEL0
ASEL
M
M
M
0
0
0
1
1
1
M
0
1
System Peripheral Clock Source
M
M
M
0
1
0
1
0
1
49.152
24.576
12.288
ACLK
Stops low all clo o cks except 20M M
PCLK1
33.3334
TEST
TEST
25.00
40.00
20.00
20.00
20.00
Revision 092799
USB Clock (MHz)
USEL
PCLK2,3
66.6667
33.3334
66.6667
M
TEST
TEST
0
1
50.00
80.00
40.00
ICS650-01
UCLK
12
24
48
Printed 11/15/00
PCLK4
TEST
TEST
25.00
25.00
18.75
20.00
25.00
25.00