mpc9773far2 Integrated Device Technology, mpc9773far2 Datasheet

mpc9773far2

Manufacturer Part Number

mpc9773far2

Description

3.3v 1 12 Lvcmos Pll Clock Generator

Manufacturer

Integrated Device Technology

Datasheet

1.MPC9773FAR2.pdf (19 pages)

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IDT™ 3.3 V 1:12 LVCMOS PLL Clock Generator

Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc

3.3 V 1:12 LVCMOS PLL Clock

Generator

Freescale Semiconductor

Technical Data

3.3 V 1:12 LVCMOS PLL Clock

Generator

for high-performance low-skew clock distribution in mid-range to high-

performance networking, computing, and telecom applications. With output

frequencies up to 240 MHz and output skews less than 250 ps the device meets

the needs of the most demanding clock applications.

Features

•

Functional Description

MPC9773 requires the connection of the PLL feedback output QFB to feedback input FB_IN to close the PLL feedback path. The

reference clock frequency and the divider for the feedback path determine the VCO frequency. Both must be selected to match

the VCO frequency range. The MPC9773 features an extensive level of frequency programmability between the 12 outputs as

well as the output to input relationships, for instance 1:1, 2:1, 3:1, 3:2, 4:1, 4:3, 5:1, 5:2, 5:3, 5:4, 5:6, 6:1, 8:1 and 8:3.

feedback frequency is independent of the output frequencies. This allows for very flexible programming of the input reference

versus output frequency relationship. The output frequencies can be either odd or even multiples of the input reference. In addi-

tion, the output frequency can be less than the input frequency for applications where a frequency needs to be reduced by a non-

binary factor. The MPC9773 also supports the 180° phase shift of one of its output banks with respect to the other output banks.

The QSYNC outputs reflect the phase relationship between the QA and QC outputs and can be used for the generation of system

baseline timing signals.

LVCMOS compatible clock inputs are provided for clock redundancy support. The PLL_EN control selects the PLL bypass con-

figuration for test and diagnosis. In this configuration, the selected input reference clock is routed directly to the output dividers,

bypassing the PLL. The PLL bypass is fully static and the minimum clock frequency specification and all other PLL characteristics

do not apply.

MPC9773. The MPC9773 has an internal power-on reset.

LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 Ω transmission

lines. For series terminated transmission lines, each of the MPC9773 outputs can drive one or two traces, giving the devices an

effective fanout of 1:24. The device is pin and function compatible to the MPC973 and is packaged in a 52-lead LQFP package.

The MPC9773 is a 3.3 V compatible, 1:12 PLL based clock generator targeted

The MPC9773 utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the

The QSYNC output will indicate when the coincident rising edges of the above relationships will occur. The selectability of the

The REF_SEL pin selects the LVPECL or the LVCMOS compatible inputs as the reference clock signal. Two alternative

The outputs can be individually disabled (stopped in logic low state) by programming the serial CLOCK_STOP interface of the

The MPC9773 is fully 3.3 V compatible and requires no external loop filter components. All inputs (except PCLK) accept

down support

52-lead Pb-free package available

1:12 PLL based low-voltage clock generator

3.3 V power supply

Internal power-on reset

Generates clock signals up to 242.5 MHz

Maximum output skew of 250 ps

Differential PECL reference clock input

Two LVCMOS PLL reference clock inputs

External PLL feedback supports zero-delay capability

Various feedback and output dividers (refer to Application Section)

Supports up to three individual generated output clock frequencies

Synchronous output clock stop circuitry for each individual output for power

Drives up to 24 clock lines

Ambient temperature range -40°C to +85°C

Pin and function compatible to the MPC973

PLL CLOCK GENERATOR

52-LEAD LQFP PACKAGE

3.3 V 1:12 LVCMOS

Pb-FREE PACKAGE

MPC9773

CASE 848D-03

FA SUFFIX

AE SUFFIX

DATA SHEET

Rev 5, 08/2005

MPC9773

Related parts for mpc9773far2

mpc9773far2 Summary of contents

Page 1

... The device is pin and function compatible to the MPC973 and is packaged in a 52-lead LQFP package. IDT™ 3.3 V 1:12 LVCMOS PLL Clock Generator © Freescale Semiconductor, Inc., 2005. All rights reserved. Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc MPC9773 3.3 V 1:12 LVCMOS ...

Page 2

... V CC INV_CLK STOP_DATA STOP_CLK MR/OE FSEL_B1 FSEL_B0 FSEL_A1 FSEL_A0 VCO_SEL MPC9773 IDT™ 3.3 V 1:12 LVCMOS PLL Clock Generator Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc 2 Ω 0 ÷4, ÷6, ÷8, ÷12 Ref ÷2 VCO 0 ÷4, ÷6, ÷8, ÷10 1 ÷1 1 ÷2, ÷4, ÷6, ÷8 PLL ÷ ...

Page 3

... See Table 3 to Table 6 IDT™ 3.3 V 1:12 LVCMOS PLL Clock Generator Advanced Clock Drivers Device Data Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc Freescale Semiconductor Type PLL reference clock Alternative PLL reference clock Differential LVPECL reference clock ...

Page 4

... MPC9773 IDT™ 3.3 V 1:12 LVCMOS PLL Clock Generator Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc 4 ) Table 5. Ouput Divider Bank QA[0:3] VCO_SEL VCO ÷ VCO ÷ VCO ÷ VCO ÷ 24 ...

Page 5

... V 3. Inputs have pull-down resistors affecting the input current. IDT™ 3.3 V 1:12 LVCMOS PLL Clock Generator Advanced Clock Drivers Device Data Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc Freescale Semiconductor Min 200 2000 ...

Page 6

... JIT(CC) (10) t Period Jitter JIT(PER) I/O Phase Jitter RMS (1 σ) t JIT(∅) MPC9773 IDT™ 3.3 V 1:12 LVCMOS PLL Clock Generator Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc 6 (1), (2) = 3.3 V ± 5 -40°C to 85°C) A Min ÷ 4 feedback 50.0 ÷ 6 feedback 33.3 ÷ ...

Page 7

... I/O jitter is valid for a VCO frequency of 400 MHz. Refer to 12. –3 dB point of PLL transfer characteristics. IDT™ 3.3 V 1:12 LVCMOS PLL Clock Generator Advanced Clock Drivers Device Data Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc Freescale Semiconductor (1), (2) = 3.3 V ± 5 -40°C to 85°C) ...

Page 8

... QC outputs 100 MHz Figure 3. Example Configuration MPC9773 IDT™ 3.3 V 1:12 LVCMOS PLL Clock Generator Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc 8 APPLICATIONS INFORMATION the specified frequency range. This divider is controlled by the VCO_SEL pin. VCO_SEL effectively extends the usable input frequency range while it has no effect on the output to reference frequency ratio ...

Page 9

... STOP_DATA IDT™ 3.3 V 1:12 LVCMOS PLL Clock Generator Advanced Clock Drivers Device Data Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc Freescale Semiconductor user may programmably enable an output clock by writing logic ‘1’ to the respective enable bit. The clock stop logic ...

Page 10

... QC(÷2) QSYNC MPC9773 IDT™ 3.3 V 1:12 LVCMOS PLL Clock Generator Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc 10 coincident rising edges of the QA and QC outputs. The duration and the placement of the pulse is dependent on QA and QC output frequencies: the QSYNC pulse width is equal to the period of the higher of the QA and QC output frequencies ...

Page 11

... IDT™ 3.3 V 1:12 LVCMOS PLL Clock Generator Advanced Clock Drivers Device Data Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc Freescale Semiconductor Using the MPC9773 in Zero-Delay Applications Nested clock trees are typical applications for the MPC9773 ...

Page 12

... FB = ÷ =÷4 0 200 250 300 VCO frequency [MHz] Figure 9. MPC9773 I/O Jitter MPC9773 IDT™ 3.3 V 1:12 LVCMOS PLL Clock Generator Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc 12 120 100 140 120 to Figure 11 to predict a ...

Page 13

... V IDT™ 3.3 V 1:12 LVCMOS PLL Clock Generator Advanced Clock Drivers Device Data Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc Freescale Semiconductor At the load end the voltage will double, due to the near unity reflection coefficient will then increment towards the quiescent 3 ...

Page 14

... MPC9773 3.3 V 1:12 LVCMOS PLL Clock Generator Pulse Generator Ω Differential Pulse Generator Ω MPC9773 IDT™ 3.3 V 1:12 LVCMOS PLL Clock Generator Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc 14 MPC9773 DUT Ω Ω Figure 15. CCLK MPC9773 AC Test Reference MPC9773 DUT = 50 Ω ...

Page 15

... The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs Figure 21. Cycle-to-Cycle Jitter IDT™ 3.3 V 1:12 LVCMOS PLL Clock Generator Advanced Clock Drivers Device Data Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc Freescale Semiconductor V CC ÷ 2 ...

Page 16

... MPC9773 3.3 V 1:12 LVCMOS PLL Clock Generator MPC9773 IDT™ 3.3 V 1:12 LVCMOS PLL Clock Generator Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc 16 PACKAGE DIMENSIONS CASE 848D-03 ISSUE F 52-LEAD LQFP PACKAGE Advanced Clock Drivers Device Data 16 NETCOM PAGE MPC9773 Freescale Semiconductor ...

Page 17

... MPC9773 3.3 V 1:12 LVCMOS PLL Clock Generator IDT™ 3.3 V 1:12 LVCMOS PLL Clock Generator Advanced Clock Drivers Device Data Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc Freescale Semiconductor PACKAGE DIMENSIONS CASE 848D-03 ISSUE F 52-LEAD LQFP PACKAGE 17 NETCOM PAGE MPC9773 ...

Page 18

... MPC9773 3.3 V 1:12 LVCMOS PLL Clock Generator MPC9773 IDT™ 3.3 V 1:12 LVCMOS PLL Clock Generator Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc 18 PACKAGE DIMENSIONS CASE 848D-03 ISSUE F 52-LEAD LQFP PACKAGE 18 NETCOM PAGE MPC9773 Advanced Clock Drivers Device Data Freescale Semiconductor ...

Page 19

... Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners ...

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