mpc9773far2 Integrated Device Technology, mpc9773far2 Datasheet - Page 13

• Manufacturer Part Number: mpc9773far2
• Description: 3.3v 1 12 Lvcmos Pll Clock Generator
• Manufacturer: Integrated Device Technology

IDT™ 3.3 V 1:12 LVCMOS PLL Clock Generator
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MPC9773
3.3 V 1:12 LVCMOS PLL Clock Generator
Advanced Clock Drivers Device Data
Freescale Semiconductor
thus only a single terminated line can be driven by each
output of the MPC9773 clock driver. For the series terminated
case, however, there is no DC current draw; thus the outputs
can drive multiple series terminated lines.
illustrates an output driving a single series terminated line
versus two series terminated lines in parallel. When taken to
its extreme the fanout of the MPC9773 clock driver is
effectively doubled due to its capability to drive multiple lines.
results of an output driving a single line versus two lines. In
both cases the drive capability of the MPC9773 output buffer
is more than sufficient to drive 50-Ω transmission lines on the
incident edge. Note from the delay measurements in the
simulations that a delta of only 43 ps exists between the two
differently loaded outputs. This suggests that the dual line
driving need not be used exclusively to maintain the tight
output-to-output skew of the MPC9773. The output waveform
in
caused by the impedance mismatch seen looking into the
driver. The parallel combination of the
36-Ω series resistor plus the output impedance does not
match the parallel combination of the line impedances. The
voltage wave launched down the two lines will equal:
Figure 13
This technique draws a fairly high level of DC current and
Figure 12. Single versus Dual Transmission Lines
The waveform plots in
In
In
MPC9773
MPC9773
Output
Output
14 Ω
14 Ω
Buffer
Buffer
shows a step in the waveform. This step is
V
Z
R
R
V
0
L
L
S
0
= V
= 50 Ω || 50 Ω
= 36 Ω || 36 Ω
= 14 Ω
= 3.0 (25 ÷ (18+17+25)
= 1.31 V
S
(Z
R
R
R
0
S
S
S
Figure 13
÷ (R
= 36 Ω
= 36 Ω
= 36 Ω
S
+ R
show the simulation
0
Z
Z
Z
O
O
O
+ Z
= 50 Ω
= 50 Ω
= 50 Ω
0
Figure 12
))
OutA
OutB0
OutB1
13
unity reflection coefficient, to 2.6 V. It will then increment
towards the quiescent 3.0 V in steps separated by one round
trip delay (in this case 4.0 ns).
1.
cause any false clock triggering; however, designers may be
uncomfortable with unwanted reflections on the line. To better
match the impedances when driving multiple lines, the
situation in
terminating resistors are reduced such that when the parallel
combination is added to the output buffer impedance, the line
impedance is perfectly matched.
At the load end the voltage will double, due to the near
Since this step is well above the threshold region it will not
3.0
2.5
2.0
1.5
1.0
0.5
Final skew data pending specification.
0
Figure 14. Optimized Dual Line Termination
Figure 13. Single versus Dual Waveforms
Figure 14
MPC9773
Output
14 Ω
Buffer
t
14 Ω + 22 Ω || 22 Ω = 50 Ω || 50 Ω
D
2
In
= 3.8956
OutA
4
should be used. In this case the series
25 Ω = 25 Ω
R
R
S
S
6
= 22 Ω
= 22 Ω
Time (ns)
t
D
= 3.9386
OutB
8
Z
Z
O
O
= 50 Ω
= 50 Ω
10
12
MPC9773
NETCOM
14
13
MPC9773