mpc9773far2 Integrated Device Technology, mpc9773far2 Datasheet - Page 15

• Manufacturer Part Number: mpc9773far2
• Description: 3.3v 1 12 Lvcmos Pll Clock Generator
• Manufacturer: Integrated Device Technology

IDT™ 3.3 V 1:12 LVCMOS PLL Clock Generator
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MPC9773
3.3 V 1:12 LVCMOS PLL Clock Generator
Advanced Clock Drivers Device Data
Freescale Semiconductor
The variation in cycle time of a signal between adjacent cycles, over a random
sample of adjacent cycle pairs
The pin-to-pin skew is defined as the worst case difference in propagation
delay between any similar delay path within a single device
The time from the PLL controlled edge to the non controlled edge,
divided by the time between PLL controlled edges, expressed as
a percentage
Figure 17. Output-to-Output Skew t
Figure 19. Output Duty Cycle (DC)
Figure 21. Cycle-to-Cycle Jitter
T
N
t
P
T
N+1
T
0
DC = t
t
SK(O)
P
/T
0
T
x 100%
JIT(CC)
Figure 23. Output Transition Time Test Reference
= |T
t
N
F
–T
V
V
GND
SK(O)
N+1
CC
CC
V
V
GND
V
V
GND
|
CC
CC
CC
CC
÷ 2
÷ 2
÷ 2
15
The deviation in cycle time of a signal with respect to the ideal period over a
random sample of cycles
CCLKx
FB_IN
The deviation in t
sample of cycles
CCLKx
FB_IN
Figure 18. Propagation Delay (t
t
R
V
CC
0.55
= 3.3 V
2.4
T
0
0
for a controlled edge with respect to a t
Figure 22. Period Jitter
Figure 20. I/O Jitter
Offset) Test Reference
t
(∅)
T
JIT(PER)
T
JIT(∅)
(∅)
= |T
, Static Phase
= |T
0
N
mean in a random
–1/f
0
-T
0
1
|
mean|
V
V
GND
V
V
GND
CC
CC
CC
CC
MPC9773
÷ 2
÷ 2
NETCOM
15
MPC9773