mc100ep446 ON Semiconductor, mc100ep446 Datasheet - Page 16

• Manufacturer Part Number: mc100ep446
• Description: 3.3v/5v 8??bit Cmos/ecl/ttl Data Input Parallel/serial Converter
• Manufacturer: ON Semiconductor

suspend all of the device activities and prevent runt pulses from being generated. The rising edge of CKEN followed by the
falling edge of CLK will suspend all activities. The falling edge of CKEN followed by the falling edge of CLK will resume
all activities (Figure 13).
framer and can help the user synchronize the serial data
output, S
Furthermore, PCLK can be used as a trigger for input
parallel data (Figure 14).
available to this device only. For single–ended input
CKSEL
The differential synchronous CKEN inputs (Pins 6 and 7), disable the internal clock circuitry. The synchronous CKEN will
The differential PCLK output (Pins 14 and 15) is a word
An internally generated voltage supply, the V
CKEN
SOUT
PCLK
CLK
OUT
Internal Clock
Disabled
(Pins 11 and 12), in their applications.
Data Format Logic
Pattern Generator
(FPGA, ASIC)
Figure 13. Timing Diagram with CKEN with CKSEL HIGH
TRIGGER
D0−1
Figure 14. PCLK as Trigger Application
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pin, is
16
Internal Clock
Enabled
conditions, the unused differential input is connected to V
as a switching reference voltage. V
coupled inputs. When used, decouple V
0.01 mF capacitor and limit current sourcing or sinking to
0.5 mA. When not used, V
outputs of the differential pair must be terminated (50 W to
V
TT
) even if only one output is used.
CLK
CLK
EP446
PCLK
D1−1
RESET
SYNC
D2−1
S
OUT
BB
SERIAL DATA
should be left open. Also, both
D3−1
BB
may also rebias AC
D4−1
BB
and V
D5−1
CC
via a
BB